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參數(shù)資料
| 型號： | CY2V9950 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 164K |
| 代理商： | CY2V9950 |
CY2V9950
Document #: 38-07436 Rev. **
Page 3 of 9
The PE pin determines whether the outputs synchronize to the
rising edge or the falling edge of the reference signal, as
indicated in
Table 5.
The CY2V9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level which is equal or
higher than that on any one of the output power supplies.
Table 6. Power Supply Constraints
VDDQ1
[7]
3.3V
3.3V or 2.5V
2.5V
Governing Agencies
The following agencies provide specifications that apply to the
CY2V9950. The agency name and relevant specification is
listed below.
Table 4. Frequency Range Select
FS
L
M
H
PLL Frequency Range
24 to 50 MHz
48 to 100 MHz
96 to 200 MHz
Table 5. PE Settings
PE
L
H
Synchronization
Negative
Positive
VDD
VDDQ3
[7]
3.3V or 2.5V
2.5V
VDDQ4
[7]
3.3V or 2.5V
2.5V
2.5V
Agency Name
JEDEC
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
1596.3 (Jiter Specs)
94 (Moisture Grading)
883E Method 1012.1 (Therma Theta JC)
IEEE
UL-194_V0
MIL
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN(MIN)
V
IN(MAX)
T
S
T
A
T
J
ESD
HBM
JC
JA
UL-94
MSL
F
IT
DC Electrical Specifications @ 2.5V
Description
Condition
Min.
2.25
2.97
Max.
2.75
3.63
–
Unit
V
V
V
V
°
C
°
C
°
C
V
°
C/W
°
C/W
Operating Voltage
Operating Voltage
Input Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
ESD Protection (Human Body Model)
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability Rating
Moisture Sensitivity Level
Failure in Time
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to V
SS
Relative to V
DD
Non Functional
Functional
Functional
MIL-STD-883, Method 3015
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
@1/8 in.
V
SS
–
0.3
–
–
65
–
40
–
2000
V
DD
+ 0.3
+150
+85
155
–
42
105
V
–
0
1
10
Manufacturing Testing
ppm
Parameter
V
DD
V
IL
V
IH
V
IHH[8]
V
IMM[8]
V
ILL[8]
I
IL
Description
Conditions
Min.
2.375
–
1.7
V
DD
–
–
0.4
V
DD
/2
–
0.2 V
DD
/2 + 0.2
–
Max.
2.625
0.7
–
–
Unit
V
V
V
V
V
V
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
2.5V ± 5%
REF, FB, PE, and sOE# Inputs
3-Level Inputs
(TEST, FS, nF[1:0])
(These pins are normally wired to
VDD,GND or unconnected)
V
IN
= V
DD
/G
ND
,V
DD
= Max
(REF, PE, and FB inputs)
0.4
Input Leakage Current
–
5
5
μ
A
Notes:
7.
VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3
= 2.5V and VDDQ4 = 2.5V.
These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
8.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2V9950AC | 制造商:Rochester Electronics LLC 功能描述:2.5/3.3V 200 MHZ LVCMOS INPUT, 8 OUTPUT ZDB - Bulk |
| CY2V9950ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V995AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
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