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參數(shù)資料
| 型號(hào)： | CY2V9950 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | CY2V9950 |
CY2V9950
Document #: 38-07436 Rev. **
Page 2 of 9
Device Configuration
The outputs of the CY2V9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1
and
2
respectively.
Table 1. Output Divider Settings
–
Bank 3
The divider settings, output frequencies, and possible config-
urations of connecting FB to ANY output are summarized in
Table 3
.
Table 3. Output Frequency Settings
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY2V9950 PLL operating frequency range that
corresponds to each FS level is given in
Table 4.
Notes:
1.
2.
‘
PD
’
indicates an internal pull-down and
‘
PU
’
indicates an internal pull-up.
‘
3
’
indicates a three-level input buffer.
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin (<0.2
”
). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
LL disables outputs if TEST = MID and sOE# = HIGH.
When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH, sOE# disables them LOW when PE = LOW.
These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency at a given
reference frequency (F
) and divider and feedback configurations. The user must select a configuration and a reference frequency that will generate a VCO
frequency that is within the range specified by FS pin. Refer to
Table 4
.
3.
4.
5.
6.
Pin Description
Pin
29
13
27
Name
REF
FB
TEST
I/O
[1]
I
I
Type
Description
LVTTL/LVCMOS
LVTTL
3-Level
Reference Clock Input
.
Feedback Input
.
When MID or HIGH, disables PLL (except for conditions of note 3)
. REF
goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable
. When HIGH, it stops clock outputs (except
2Q0 and 2Q1) in a LOW state (for PE = H or M)
–
2Q0 and 2Q1 may be
used as the feedback signal to maintain phase lock. When TEST is held at
MID level and sOE# is high, the nF[1:0] pins act as output disable controls
for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low output
drive strength
. When LOW / HIGH the outputs are synchronized with the
negative/positive edge of the reference clock. Please see
Table 5
.
Select frequency of the outputs
. Please see
Tables 1
and
2.
I
22
sOE#
I, PD
2-Level
4
PE
I, PU
LVTTL
24, 23, 26,
25, 1, 32, 3, 2
31
19, 20, 15,
16,10,11, 6, 7
21
nF[1:0]
I
3-Level
FS
nQ[1:0]
I
3-Level
LVTTL
Selects VCO operating frequency range
. Please see
Table 4
.
Four banks of two outputs
. Please see
Tables 1
and
2
for frequency
settings.
Power supply for Bank 1 and Bank 2 output buffers
. Please see
Table 6
for supply level constraints
Power supply for Bank 3 output buffers
. Please see
Table 6
for supply
level constraints
Power supply for Bank 4 output buffers
. Please see
Table 6
for supply
level constraints
Power supply for internal circuitry
. Please see
Table 6
for supply level
constraints
Ground
.
O
VDDQ1
[2]
PWRPower
12
VDDQ3
[2]
PWRPower
5
VDDQ4
[2]
PWRPower
14,30
VDD
[2]
PWRPower
8, 9, 17, 18,
28
VSS
PWRPower
3F[1:0]
LL
[4]
HH
Other
K
–
Bank3 Output Divider
2
4
1
Table 2. Output Divider Settings
–
Bank 4
4F[1:0]
LL
[4]
HH
Other
M
–
Bank4 Output Divider
2
Inverted
[5]
1
Configuration
FB to
1Qn, 2Qn
3Qn
4Qn
Output Frequency
3Q
(1/K) x F
REF
F
REF
(M/K) x F
REF
1Q, 2Q
[6]
F
REF
K x F
REF
M x F
REF
4Q
(1/M) x F
REF
(K/M) x F
REF
F
REF
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY2V9950AC | 制造商:Rochester Electronics LLC 功能描述:2.5/3.3V 200 MHZ LVCMOS INPUT, 8 OUTPUT ZDB - Bulk |
| CY2V9950ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V995AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
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