參數(shù)資料
型號(hào)： CY28412
英文描述： Clocks and Buffers
中文描述： 時(shí)鐘和緩沖器
文件頁(yè)數(shù)： 3/48頁(yè)
文件大?。?/td> 538K
代理商： CY28412
CY28405-2
Document #: 38-07511 Rev. *C
Page 3 of 16
Table 1. Frequency Select Table (FS_A FS_B)
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in
Table 3
.
The block write and block read protocol is outlined in
Table 4
while
Table 5
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
FS_A
0
0
0
1
1
FS_B
0
B6b7
1
0
B6b7
CPU
100 MHz
REF/N
200 MHz
133 MHz
Hi-Z
SRC
3V66
66 MHz
REF/N
66 MHz
66 MHz
Hi-Z
PCIF/PCI
33 MHz
REF/N
33 MHz
33 MHz
Hi-Z
REF0
14.3 MHz
REF/N
14.3 MHz
14.3 MHz
Hi-Z
REF1
14.31 MHz
REF/N
14.31 MHz
14.31 MHz
Hi-Z
USB/DOT
48 MHz
REF/N
48 MHz
48 MHz
Hi-Z
100/200 MHz
REF/N
100/200 MHz
100/200 MHz
Hi-Z
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
0
0
1
FS_B
0
1
0
CPU
200 MHz
400 MHz
266 MHz
SRC
3V66
66 MHz
66 MHz
66 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
REF0
14.3 MHz
14.3 MHz
14.3 MHz
REF1
14.31 MHz
14.31 MHz
14.31 MHz
USB/DOT
48 MHz
48 MHz
48 MHz
100/200 MHz
100/200 MHz
100/200 MHz
Table 3. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
2:8
9
10
11:18
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
19
19
20
20:27
28
29:36
37
38:45
46
....
21:27
28
29
30:37
38
39:46
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