參數(shù)資料
型號: CY28412
英文描述: Clocks and Buffers
中文描述: 時鐘和緩沖器
文件頁數(shù): 14/48頁
文件大?。?/td> 538K
代理商: CY28412
CY28405-2
Document #: 38-07511 Rev. *C
Page 14 of 16
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
ENABLE/DISABLE and SET-UP
T
STABLE
T
SS
T
SH
Clock Stabilization from Power-up
Stopclock Set-up Time
Stopclock Hold Time
1.8
ms
ns
ns
10.0
0
Table 7. Group Timing Relationship and Tolerances
Group
3V66 to PCI
Conditions
3V66 Leads PCI
Offset
Min.
1.5ns
Max.
3.5ns
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
Table 8. USB to DOT Phase Offset
Parameter
DOT Skew
USB Skew
VCH SKew
Typical
180°
Value
0.0ns
0.0ns
0.0ns
Tolerance
1000ps
1000ps
1000ps
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
3V66 Clocks
USB Clock
DOT Clock
REF Clock
Max Load
30
30
20
10
30
Units
pF
pF
pF
pF
pF
CPUT
T
PCB
T
PCB
CPUC
33
33
49.9
49.9
Measurement
Point
2pF
475
IREF
Measurement
Point
2pF
Figure 7. 0.7V Load Configuration
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