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參數(shù)資料
| 型號： | CY28405-3 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 37/48頁 |
| 文件大小： | 538K |
| 代理商： | CY28405-3 |
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CY28405-2
Document #: 38-07511 Rev. *C
Page 5 of 16
Byte 1: Control Register
Bit
7
@Pup
0
Name
Description
SRCT
SRCC
SRCT
SRCC
Reserved
Reserved
Reserved
CPUT_ITP, CPUC_ITP
Allow control of SRC during SW PCI_STP assertion
0 = Free Running, 1 = Stopped with SW PCI_STP
SRC Output Enable
0 = Disabled (three-state), 1 = Enabled
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
CPU_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPUT/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
6
1
5
4
3
2
1
1
1
1
1
1
CPUT1, CPUC1
0
1
CPUT0, CPUC0
Byte 2: Control Register
Bit
7
@Pup
0
Name
Description
SRCT, SRCC
SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
SRC Stop drive mode
0 = Driven in PCI_STP, 1 = three-state in power-down
CPU(T/C)_ITP Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
6
0
SRCT, SRCC
5
0
CPUT_ITP, CPUC_ITP
4
0
CPUT1, CPUC1
3
0
CPUT0, CPUC0
2
1
0
0
0
0
Reserved
Reserved
Reserved
Byte 3: Control Register
Bit
7
@Pup
1
Name
Description
SW PCI STOP
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Reserved
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
6
5
1
1
Reserved
PCI5
4
1
PCI4
3
1
PCI3
2
1
PCI2
1
1
PCI1
0
1
PCI0
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PDF描述 |
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| CY28412 | Clocks and Buffers |
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| CY28510 | Clocks and Buffers |
| CY2901CDC | Microprocessor Slice |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28405OC | 制造商:Cypress Semiconductor 功能描述: |
| CY28405OC-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC-2T | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 865 AND 875 CHIPSETS (CK409) - Bulk |
| CY28405OC-3 | 制造商:Rochester Electronics LLC 功能描述:CLOCK SYNTHESIZER WITH DIFFERENTIAL SRC & CPU OUT - Bulk |
| CY28405OC-3T | 制造商:Rochester Electronics LLC 功能描述:CLOCK SYNTHESIZER WITH DIFFERENTIAL SRC & CPU OUT - Bulk |
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