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參數(shù)資料
| 型號： | CY28405-3 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 538K |
| 代理商： | CY28405-3 |
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CY28405-2
Document #: 38-07511 Rev. *C
Page 4 of 16
Byte Configuration Map
....
....
....
....
....
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
47
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
48:55
56
....
....
....
Table 4. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Description
Block Read Protocol
Description
Bit
Bit
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Description
Byte Read Protocol
Description
Bit
1
2:8
9
10
11:18
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
19
19
20
20:27
28
29
21:27
28
29
30:37
38
39
Byte 0: Control Register
Bit
7
6
@Pup
0
1
Name
Description
Reserved
PCIF
PCI
Reserved, set = 0
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
Reserved, set = 0
Reserved, set = 0
Reserved, set = 1
Reserved, set = 1
Power-up latched value of FS_B pin
Power-up latched value of FS_A pin
5
4
3
2
1
0
0
0
1
1
Reserved
Reserved
Reserved
Reserved
FS_B
FS_A
HW
HW
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28405OC | 制造商:Cypress Semiconductor 功能描述: |
| CY28405OC-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC-2T | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 865 AND 875 CHIPSETS (CK409) - Bulk |
| CY28405OC-3 | 制造商:Rochester Electronics LLC 功能描述:CLOCK SYNTHESIZER WITH DIFFERENTIAL SRC & CPU OUT - Bulk |
| CY28405OC-3T | 制造商:Rochester Electronics LLC 功能描述:CLOCK SYNTHESIZER WITH DIFFERENTIAL SRC & CPU OUT - Bulk |
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