- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366977 > CY28405-3 Clocks and Buffers PDF資料下載
參數(shù)資料
| 型號(hào)： | CY28405-3 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 538K |
| 代理商： | CY28405-3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
CY28405-2
Document #: 38-07511 Rev. *C
Page 8 of 16
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tative loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
CL ...................................................Crystal load capacitance
CLe .........................................Actual loading seen by crystal
......................................using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs..............................................Stray capacitance (trace,etc)
Ci ............. Internal capacitance (lead frame, bond wires etc)
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low ‘stopped’ state.
PD# – Assertion
When PD# is sampled low by two consecutive rising edges of
CPUC clock then all clock outputs (except CPU) clocks must
be held low on their next high to low transition. CPU clocks
must be hold with CPU clock pin driven high with a value of 2x
Iref and CPUC undriven.
Due to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete.
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
(CY28405-2)
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce
= 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28412 | Clocks and Buffers |
| CY28419 | Clocks and Buffers |
| CY28510 | Clocks and Buffers |
| CY2901CDC | Microprocessor Slice |
| CY2901CDMB | Microprocessor Slice |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28405OC | 制造商:Cypress Semiconductor 功能描述: |
| CY28405OC-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC-2T | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 865 AND 875 CHIPSETS (CK409) - Bulk |
| CY28405OC-3 | 制造商:Rochester Electronics LLC 功能描述:CLOCK SYNTHESIZER WITH DIFFERENTIAL SRC & CPU OUT - Bulk |
| CY28405OC-3T | 制造商:Rochester Electronics LLC 功能描述:CLOCK SYNTHESIZER WITH DIFFERENTIAL SRC & CPU OUT - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。