參數(shù)資料
型號(hào): CY28346ZXCT
廠商: Silicon Laboratories Inc
文件頁數(shù): 17/19頁
文件大?。?/td> 0K
描述: IC CLOCK DIFF OUT CK408 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
類型: *
PLL:
輸入: 晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
其它名稱: SLCY28346ZXCT
CY28346
........................Document #: 38-07331 Rev. *C Page 7 of 19
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
1. Output impedance of the current mode buffer circuit—Ro
2. Minimum and maximum required voltage operation range
of the circuit—Vop (see Figure 4).
3. Series resistance in the buffer circuit—Ros (see Figure 4).
4. Current accuracy at given configuration into nominal test
load for given configuration.
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
2.4V
0.4V
3.3V
0V
Tr
Tf
1.5V
3.3V signals
tDC
Probe
Output under Test
Load Cap
-
Figure 3. For Single-ended Output Signals
1.2V
0V
Iout
Ros
Ro
VDD3 (3.3V +/- 5%)
Vout = 1.2V max
Vout
Slope ~ 1/R
0
Figure 4. Buffer Characteristics
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