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參數(shù)資料
| 型號(hào)： | CY28159 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 144K |
| 代理商： | CY28159 |
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CY28159
Document #: 38-07118 Rev. *A
Page 9 of 13
Notes:
9.
This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1
μ
s duration, with a crystal center frequency of
14.31818 MHz.
10. All outputs loaded as per
Table 3
, see
Figure 2
.
11.
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for CPU[(0:7), (0:7)#] signals
(see
Figure 3
).
12. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see
Figure 3
).
13. This measurement is applicable with Spread ON or Spread OFF.
14. Probes are placed on the pins, and measurements are acquired at 2.4V (see
Figure 3
).
15. Probes are placed on the pins, and measurements are acquired at 0.4V. (see
Figure 3
).
16. As this function is available through SEL(0,1), therefore, the time specified is guaranteed by design.
17. Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
AC Parameters
(V
DD
= V
DDA
= 3.3V ±5%, T
A
= 0°C to +70°C)
Symbol
Description
133 MHz Host
100 MHz Host
Unit
Notes
Min.
Max.
Min.
Max.
CPU
7.35
TPeriod
CPU(0:7), (0:7)#) Period
7.65
9.85
10.2
ns
10,12
Tr/Tf
CPU[(0:7), (0:7)#] Rise and Fall Times
175
700
175
700
ps
10,11
TSKEW1
Skew from Any CPU Pair to Any CPU Pair
100
100
ps
10,12,13
TCJJ
CPU[(0:7), (0:7)#] Cycle to Cycle Jitter
150
150
ps
10,12,13
Vover
CPU[(0:7), (0:7)#] Overshoot
Voh + 0.2
Voh + 0.2
V
10,17
Vunder
CPU[(0:7), (0:7)#] Undershoot
–0.2
-0.2
V
10,17
Vcrossover
CPU(0:7), to CPU(0:7)# Crossover Point
45%Voh
55%Voh
45%Voh
55%Voh
V
9, 10,12
Tduty
Duty Cycle
45
55
45
55
%
10,12
33MHz
15.0
Tperiod
3V33 Period
16.0
15.0
15.2
ns
10,12
THIGH
3V33 High Time
5.25
5.25
ns
10,14
TLOW
3V33 Low Time
5.05
5.05
ns
10,15
Tr/Tf
3V33 Rise and Fall Times
0.5
2.0
0.5
2.0
ns
10,11
TCCJ
3V33 Cycle to Cycle Jitter
300
-
300
ps
10,12,13
Tduty
Duty Cycle
45
55
45
55
%
10,12
REF
69.8412
Tperiod
REF Period
71.0
69.8413
71.0
nS
10,12
Tr/Tf
REF Rise and Fall Times
1.0
4.0
1.0
4.0
nS
10,11
TCCj
REF Cycle to Cycle Jitter
1000
1000
pS
10,12
Tduty
Duty Cycle
45
55
45
55
%
10,12
48MHz
45
TDC
48MHz(0,1) Duty Cycle
55
45
55
%
10,12
Tperiod
48MHz(0.1) Period
20.8299
20.8333
20.8299
20.8333
ns
10,12
Tr/Tf
48MHz(0,1) Rise and Fall Times
1.0
4.0
1.0
4.0
ps
10,11
TCCJ
48MHz(0,1) Cycle to Cycle Jitter
500
500
ps
10,12
Zout
48MHz Buffer Output Impedance
20
20
tpZL, tpZH
Output Enable Delay (all outputs)
1.0
10.0
1.0
10.0
ns
16
tpLZ, tpZH
Output Disable Delay (all outputs)
1.0
10.0
1.0
10.0
ns
16
tstable
All Clock Stabilization from Power-up
3
3
ms
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