參數(shù)資料
型號(hào)： CY27EE16ZEI
廠商： Cypress Semiconductor Corp.
英文描述： 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM
中文描述： 1鎖相環(huán)在系統(tǒng)可編程時(shí)鐘發(fā)生器與個(gè)人16K的EEPROM的
文件頁(yè)數(shù)： 9/17頁(yè)
文件大?。?/td> 163K
代理商： CY27EE16ZEI
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 9 of 17
Clock Output Settings
CLKSRC - Clock Output Crosspoint Switch Matrix
[44H(7..0)], [45H(7..0)], [46H(7..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint
switch matrix defines which source is attached to each
individual clock output. CLKSRC(2..0) is set in Registers 44H,
45H, and 46H. The remainder of registers 45H(3:1) and
46H(2:0) must be written with the values stated in the register
table when writing register values 45H(7:4), 45H(0), and
46H(7:3).
When DIV1N is divisible by 4, then CLKSRC(0,1,0) is
guaranteed
to
be
rising
CLKSRC(0,0,1). When DIV1N is 6, then CLKSRC(0,1,1) is
guaranteed
to
be
rising
CLKSRC(0,0,1).
edge
phase-aligned
with
edge
phase-aligned
with
When DIV2N is divisible by 4, then CLKSRC(1,0,1) is
guaranteed
to
be
rising
CLKSRC(1,0,0). When DIV2N is divisible by 8, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
edge
phase-aligned
with
CLKOE - Clock Output Enable Control [09H(7..0)]
Each clock output has its own output enable, CLKOE,
controlled by register 09H(7..0). To enable an output, set the
corresponding CLKOE bit to 1. CLKOE settings are in
Table 14
.
Test, Reserved, and Blank Registers
Writing to any of the following registers will cause the part to
exhibit abnormal behavior:
[00H to 08H] – Reserved
[0AH to 0BH] – Reserved
[0DH to 0FH] –Reserved
[15H to 3FH] –Reserved
[43H] –Reserved
[48H to FFH] –Reserved
Table 12. Clock Output Settings – Clock Source CLKSRC[2:0]
CLKSRC2
0
0
CLKSRC1
0
0
CLKSRC0
0
1
Definition and Notes
Reference Input
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
Reserved – Do not use
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
1
Table 13. CLKSRC Registers
Address
44H
D7
D6
D5
D4
D3
D2
D1
D0
CLKSRC2
for CLOCK1
CLKSRC0
for CLOCK3
CLKSRC1
for CLOCK5
CLKSRC1
for CLOCK1
CLKSRC2
for CLOCK4
CLKSRC0
for CLOCK5
CLKSRC0
for CLOCK1
CLKSRC1
for CLOCK4
CLKSRC2
for CLOCK6
CLKSRC2
for CLOCK2
CLKSRC0
for CLOCK4
CLKSRC1
for CLOCK6
CLKSRC1
for CLOCK2
1
CLKSRC0
for CLOCK2
1
CLKSRC2
for CLOCK3
1
CLKSRC1
for CLOCK3
CLKSRC2
for CLOCK5
1
45H
46H
CLKSRC0
for CLOCK6
1
1
Table 14. CLKOE Bit Setting
Address
09H
D7
0
D6
D5
D4
0
D3
D2
D1
CLKOE for
CLOCK6
CLKOE for
CLOCK5
CLKOE for
CLOCK4
CLKOE for
CLOCK3
CLKOE for
CLOCK2
CLKOE for
CLOCK1
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CY27EE16ZEI-XXX 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM
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