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參數(shù)資料
| 型號(hào)： | CY27EE16ZEI |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| 中文描述： | 1鎖相環(huán)在系統(tǒng)可編程時(shí)鐘發(fā)生器與個(gè)人16K的EEPROM的 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 163K |
| 代理商： | CY27EE16ZEI |
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 4 of 17
Table 2. Summary Table – CY27EE16ZE Programmable Registers
CY27EE16ZE Frequency Calculation and
Register Definitions
The CY27EE16ZE is an extremely flexible clock generator
with four basic variables that can be used to determine the final
output frequency. They are the input reference frequency
(REF), the internally calculated P and Q dividers, and the post
divider, which can be a fixed or calculated value. There are
three basic formulas for determining the final output frequency
of a CY27EE16ZE-based design. Any one of these three
formulas may be used:
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF
The basic PLL block diagram is shown in
Figure 2
. Each of the
six clock outputs on the CY27EE16ZE has a total of seven
output options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF*P)/Q) or to the
reference frequency directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the reference frequency
directly to the crosspoint switch matrix.
Register
09H
OCH
Description
CLKOE control
DIV1SRC mux and
DIV1N divider
Input Pin Control
Registers
Write Protect
Registers
Input crystal oscillator
drive control
D7
D6
CLOCK6
D5
CLOCK5
DIV1N(5)
D4
D3
CLOCK4
DIV1N(3)
D2
CLOCK3
DIV1N(2)
D1
CLOCK2
DIV1N(1)
D0
CLOCK1
DIV1N(0)
0
0
DIV1SRC DIV1N(6)
DIV1N(4)
10H
OESrc
OE0PadS
el[1]
OE0PadS
el[0]
OE1PadS
el[1]
MemWP
OE1PadS
el[0]
WPSrc
PDMEna-
ble
WPPad-
Sel[2]
0
PDMPad-
Sel[1]
WPPad-
Sel[1]
0
PDMPad-
Sel[0]
WPPad-
Sel[0]
0
11H
12H
FTAAd-
drSrc(1)
default=0
Cap-
Load(7)
ADCEn-
able
1
PB(7)
PO
FTAAd-
drSrc(0)
default=0
Cap-
Load(6)
AD-
CBypCnt
1
PB(6)
Q(6)
XCapSrc
default=1
XDRV(1)
XDRV(0)
13H
Input load capacitor
control
ADC Register
Cap-
Load(5)
ADC-
Cnt[2]
0
PB(5)
Q(5)
Cap-
Load(4)
ADC-
Cnt[1]
Pump(2)
PB(4)
Q(4)
Cap-
Load(3)
ADC-
Cnt[0]
Pump(1)
PB(3)
Q(3)
Cap-
Load(2)
ADCFilt[1] ADCFilt[0]
Cap-
Load(1)
Cap-
Load(0)
0
14H
40H
41H
42H
Charge Pump and PB
counter
Pump(0)
PB(2)
Q(2)
PB(9)
PB(1)
Q(1)
PB(8)
PB(0)
Q(0)
PO counter, Q
counter
Crosspoint switch
matrix control
44H
CLKSRC2
for
CLOCK1
CLKSRC0
for
CLOCK3
CLKSRC1
for
CLOCK5
DIV2SRC DIV2N(6)
CLKSRC1
for
CLOCK1
CLKSRC2
for
CLOCK4
CLKSRC0
for
CLOCK5
CLKSRC0
for
CLOCK1
CLKSRC1
for
CLOCK4
CLKSRC2
for
CLOCK6
DIV2N(5)
CLKSRC2
for
CLOCK2
CLKSRC0
for
CLOCK4
CLKSRC1
for
CLOCK6
DIV2N(4)
CLKSRC1
for
CLOCK2
1
CLKSRC0
for
CLOCK2
1
CLKSRC2
for
CLOCK3
1
CLKSRC1
for
CLOCK3
CLKSRC2
for
CLOCK5
1
45H
46H
CLKSRC0
for
CLOCK6
DIV2N(3)
1
1
47H
DIV2SRC mux and
DIV2N divider
DIV2N(2)
DIV2N(1)
DIV2N(0)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY27EE16ZEI-XXX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16ZEI-XXXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27H010-25HC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| CY27H010-25JC | 制造商:Cypress Semiconductor 功能描述: |
| CY27H010-25ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 8 High-Speed CMOS EPROM |
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