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參數(shù)資料
| 型號： | CY27EE16ZEI |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| 中文描述： | 1鎖相環(huán)在系統(tǒng)可編程時鐘發(fā)生器與個人16K的EEPROM的 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 163K |
| 代理商： | CY27EE16ZEI |
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 8 of 17
PLL Post Divider Options
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal
feeding into the divider banks is the calculated VCO frequency
or REF. There are 2 select muxes (DIV1SRC and DIV2SRC)
and 2 divider banks (Divider Bank 1 and Divider Bank 2) used
to determine this clock signal. The clock signals passing
through DIV1SRC and DIV2SRC are referred to as DIV1CLK
and DIV2CLK, respectively.
The divider banks have 4 unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-
dently programmed (DIV1N and DIV2N) for each of the 2
divider banks. The minimum value of DIVxN is 4. The
maximum value of DIVxN is 127. A value of DIVxN below 4 is
not guaranteed to work properly.
DIV1SRC is a single bit variable, controlled by register OCH.
The remaining 7 bits of register OCH determine the value of
post divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H.
The remaining 7 bits of register 47H determine the value of
post divider DIV2N.
Register OCH and 47H are defined in
Table 9
.
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
are dependent on internal variable PB (see section "[00H to
08H] – Reserved [0AH to 0BH] – Reserved [0DH to 0FH]
–Reserved [15H to 3FH] –Reserved [43H] –Reserved [48H to
FFH] –Reserved", page 9).
Table 10
summarizes the proper
charge pump settings, based on P
total
. See
Table 11
, "Register
40H Change Pump Bit Settings", page 8, for register 40H bit
locations.
Although using
Table 11
will guarantee stability, it is recom-
mended to use the Print Preview function in CyberClocks to
determine the ideal charge pump settings for optimal jitter
performance.
PLL stability cannot be guaranteed for P
total
values below 16
and above 1023. If P
total
values above 1023 are needed, use
CyberClocks to determine the best charge pump setting.
Table 9. PLL Post Divider Options
Address
OCH
47H
D7
D6
D5
D4
D3
D2
D1
D0
DIV1SRC
DIV2SRC
DIV1N(6)
DIV2N(6)
DIV1N(5)
DIV2N(5)
DIV1N(4)
DIV2N(4)
DIV1N(3)
DIV2N(3)
DIV1N(2)
DIV2N(2)
DIV1N(1)
DIV2N(1)
DIV1N(0)
DIV2N(0)
Table 10. Charge Pump Settings
Charge Pump Setting
– Pump(2..0)
000
001
010
011
100
101, 110, 111
Calculated P
total
16 – 44
45 – 479
480 – 639
640 – 799
800 – 1023
Do Not Use – device will be unstable
Table 11. Register 40H Change Pump Bit Settings
Address
40H
D7
1
D6
1
D5
0
D4
D3
D2
D1
D0
Pump(2)
Pump(1)
Pump(0)
PB(9)
PB(8)
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PDF描述 |
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| CY27H010-25HC | x8 EPROM |
| CY27H010-30HC | x8 EPROM |
| CY27H010-35HC | x8 EPROM |
| CY27H010-35HMB | x8 EPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY27EE16ZEI-XXX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16ZEI-XXXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27H010-25HC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| CY27H010-25JC | 制造商:Cypress Semiconductor 功能描述: |
| CY27H010-25ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 8 High-Speed CMOS EPROM |
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