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參數資料
| 型號： | CY23S09SXC-1T |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, MS-012, SOIC-16 |
| 文件頁數： | 4/10頁 |
| 文件大?。?/td> | 295K |
| 代理商： | CY23S09SXC-1T |
CY23S09, CY23S05
Document Number: 38-07296 Rev. *F
Page 3 of 10
Table 1. Pin Description for CY23S09
Pin
Signal
Description
1REF[2]
Input reference frequency, 5V tolerant input
2
CLKA1[3]
Buffered clock output, bank A
3
CLKA2[3]
Buffered clock output, bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[3]
Buffered clock output, bank B
7
CLKB2[3]
Buffered clock output, bank B
8S2[4]
Select input, bit 2
9S1[4]
Select input, bit 1
10
CLKB3[3]
Buffered clock output, bank B
11
CLKB4[3]
Buffered clock output, bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[3]
Buffered clock output, bank A
15
CLKA4[3]
Buffered clock output, bank A
16
CLKOUT[3]
Buffered output, internal feedback on this pin
Table 2. Pin Description for CY23S05
Pin
Signal
Description
1REF[2]
Input reference frequency, 5V tolerant input
2CLK2[3]
Buffered clock output
3CLK1[3]
Buffered clock output
4
GND
Ground
5CLK3[3]
Buffered clock output
6VDD
3.3V supply
7CLK4[3]
Buffered clock output
8
CLKOUT[3]
Buffered clock output, internal feedback on this pin
Notes
2. Weak pull down.
3. Weak pull down on all outputs.
4. Weak pull up on these inputs.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY23S09ZC-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY23S09ZC-1H | 制造商:Cypress Semiconductor 功能描述: |
| CY23S09ZXC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Cost 3.3V Spread Aware Zero Delay Buffer |
| CY23S09ZXC1H | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 16-Pin TSSOP |
| CY23S09ZXC-1H | 功能描述:鎖相環(huán) - PLL 3.3V ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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