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參數(shù)資料
| 型號： | CY23S09SXC-1T |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, MS-012, SOIC-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 295K |
| 代理商： | CY23S09SXC-1T |
CY23S09, CY23S05
Document Number: 38-07296 Rev. *F
Page 2 of 10
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Because the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT is
not used, it must have a capacitive load equal to that on other
outputs, to obtain zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate
loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information, refer to the application note “CY23S05
and CY23S09 as PCI and SDRAM Buffers.”
Spread Aware
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation. Cypress is one
of the pioneers of SSFTG development and designed this
product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is
not designed to pass the SS feature through, the result is a signif-
icant amount of tracking skew, which may cause problems in
systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress application note AN1278, EMI Suppression
Techniques with Spread Spectrum Frequency Timing Generator
(SSFTG) ICs.
Pinouts
Figure 1. Pin Configuration – CY23S09
Figure 2. Pin Configuration – CY23S05
Select Input Decoding for CY23S09
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[1]
Output Source
PLL Shutdown
0
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Reference
Y
1
Driven
PLL
N
Note
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23S09ZC-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY23S09ZC-1H | 制造商:Cypress Semiconductor 功能描述: |
| CY23S09ZXC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Cost 3.3V Spread Aware Zero Delay Buffer |
| CY23S09ZXC1H | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 16-Pin TSSOP |
| CY23S09ZXC-1H | 功能描述:鎖相環(huán) - PLL 3.3V ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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