參數(shù)資料
型號(hào): CY2DP818ZXCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 2DP SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO38
封裝: 4.40 MM, LEAD FREE, TSSOP-38
文件頁數(shù): 1/7頁
文件大?。?/td> 239K
代理商: CY2DP818ZXCT
CY2DP818
1:8 Clock Fanout Buffer
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-07061 Rev. *B
Revised August 5, 2009
Features
Low-voltage operation VDD = 3.3V
1:8 fanout
Operation to 350 MHz
Single input configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50 ohm load
Low input capacitance
Low output skew
Low propagation delay (tpd = 4 ns, typical)
Commercial and Industrial temperature ranges
38-Pin TSSOP Package
Description
The Cypress CY2DP818 fanout buffer features a single LVDS or
a single ended LVTTL compatible input and eight LVPECL output
pairs.
Designed
for
data-communications
clock
management
applications, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from single
ended to LVPECL and/or for the distribution of LVPECL based
clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the InConfig pin for single ended or
differential input.
Logic Block Diagram
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
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