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參數(shù)資料
| 型號： | CXK79M72C161GB |
| 英文描述： | MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| 中文描述： | 內(nèi)存SigmaRAM 16Meg 1x1的LVCMOS的I / O（256 × 72）（27頁364K牧師7/6/01） |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 554K |
| 代理商： | CXK79M72C161GB |
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SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
19 / 30
July 19, 2002
Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, con-
troller, etc.), SRAMs, other components, and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP
Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
The TAP consists of the following four signals:
TCK:
Test Clock
Induces (clocks) TAP Controller state transitions.
TMS:
Test Mode Select
Inputs commands to the TAP Controller. Sampled on the rising edge of TCK.
TDI:
Test Data In
Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK.
TDO:
Test Data Out
Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
WhenJTAGisnotused,TCKshouldbetied“l(fā)ow”topreventclockingtheSRAM.TMSandTDIshouldeitherbetied“high”
through a pull-up resistor or left unconnected. TDO should be left unconnected.
Note
: Operation of the TAP does not disrupt normal SRAM operation except when the EXTEST-A or SAMPLE-Z instruc-
tion is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the
functionality of the device.
JTAG DC Recommended Operating Conditions
(V
DD
= 1.8V ± 0.1V, T
A
= 0 to 85
°
C
)
JTAG AC Test Conditions
(V
DD
= 1.8V ± 0.1V, T
A
= 0 to 85
°
C
)
Parameter
Symbol
Test Conditions
Min
Max
Units
JTAG Input High Voltage (TCK, TMS, TDI)
V
TIH
---
V
DD
/2 + 0.3
V
DD
+ 0.3
V
JTAG Input Low Voltage (TCK, TMS, TDI)
V
TIL
---
-0.3
V
DD
/2 - 0.3
V
JTAG Output High Voltage (TDO)
V
TOH
I
TOH
= -100uA
V
DD
- 0.1
---
V
JTAG Output Low Voltage (TDO)
V
TOL
I
TOL
= 100uA
---
0.1
V
JTAG Output High Voltage (TDO)
V
TOH
I
TOH
= -8mA
V
DD
- 0.4
---
V
JTAG Output Low Voltage (TDO)
V
TOL
I
TOL
= 8mA
---
0.4
V
JTAG Input Leakage Current
I
TLI
V
TIN
= V
SS
to V
DD
-20
10
uA
JTAG Output Leakage Current
I
TLO
V
TOUT
= V
SS
to V
DD
-10
10
uA
Parameter
Symbol
Conditions
Units
Notes
JTAG Input High Level
V
TIH
1.8
V
JTAG Input Low Level
V
TIL
0.0
V
JTAG Input Rise & Fall Time
1.0
V/ns
JTAG Input Reference Level
0.9
V
JTAG Output Reference Level
0.9
V
JTAG Output Load Condition
See Fig. 1 (page 15)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK79M72C164GB | MEMORY-SigmaRAM 16Meg 1x1z HSTL I/O (256K x 72) (27 pages 368K Rev. 7/6/01) |
| CXK79M72C165GB | MEMORY-SigmaRAM 16Meg 1x1z LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| CXO-M10 | Telecommunication IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK79M72C164GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) |
| CXK79M72C165GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) |
| CXK79M72C165GB-4 | 制造商:SONY 功能描述: |
| CXK900L-S | 制造商:CHDS 功能描述:HEAT SINK 130x30x10mm |
| CX-L0612A | 制造商:KYOCERA Corporation 功能描述:INVERTER FOR 5.7" DISPLAYS |
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