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| 型號(hào)： | CXK79M72C161GB |
| 英文描述： | MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| 中文描述： | 內(nèi)存SigmaRAM 16Meg 1x1的LVCMOS的I / O（256 × 72）（27頁(yè)364K牧師7/6/01） |
| 文件頁(yè)數(shù)： | 13/30頁(yè) |
| 文件大小： | 554K |
| 代理商： | CXK79M72C161GB |
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SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
13 / 30
July 19, 2002
AC Electrical Characteristics
(
V
DD
= 1.8V
±
0.1V, V
SS
= 0V, T
A
= 0 to 85
o
C)
Allparameters aremeasuredfromthemid-pointoftheobjectsignaltothemid-pointofthereferencesignal,unlessotherwisenoted.
1. These parameters apply to control inputs E1, E2, E3, ADV, W, and Bx.
2. These parameters are guaranteed by design through extensive corner lot characterization.
3. These parameters are measured at
±
50mV from steady state voltage.
Parameter
Symbol
-33
-4
-5
Units
Notes
Min
Max
Min
Max
Min
Max
Input Clock Cycle Time
t
KHKH
3.3
---
4.0
---
5.0
---
ns
Input Clock High Pulse Width
t
KHKL
1.3
---
1.5
---
2.0
---
ns
Input Clock Low Pulse Width
t
KLKH
1.3
---
1.5
---
2.0
---
ns
Address Input Setup Time
t
AVKH
0.7
---
0.8
---
1.0
---
ns
Address Input Hold Time
t
KHAX
0.4
---
0.5
---
0.5
---
ns
Control Input Setup Time
t
BVKH
0.7
---
0.8
---
1.0
---
ns
1
Control Input Hold Time
t
KHBX
0.4
---
0.5
---
0.5
---
ns
1
Data Input Setup Time
t
DVKH
0.7
---
0.8
---
1.0
---
ns
Data Input Hold Time
t
KHDX
0.4
---
0.5
---
0.5
---
ns
Input Clock High to Output Data Valid
t
KHQV
---
1.8
---
2.1
---
2.3
ns
Input Clock High to Output Data Hold
t
KHQX
0.5
---
0.5
---
0.5
---
ns
2
Input Clock High to Output Data Low-Z
t
KHQX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Data High-Z
t
KHQZ
---
1.8
---
2.1
---
2.3
ns
2,3
Input Clock High to Output Clock High
t
KHCH
0.5
1.8
0.5
2.1
0.5
2.3
ns
Input Clock High to Output Clock Low-Z
t
KHCX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Clock High-Z
t
KHCZ
---
1.8
---
2.1
---
2.3
ns
2,3
Output Clock High to Output Data Valid
t
CHQV
---
0.4
---
0.5
---
0.6
ns
2
Output Clock High to Output Data Hold
t
CHQX
-0.4
---
-0.5
---
-0.6
---
ns
2
Output Clock High Pulse Width
t
CHCL
t
KHKL
±
0.2
t
KHKL
±
0.2
t
KHKL
±
0.2
ns
2
Output Clock Low Pulse Width
t
CLCH
t
KLKH
±
0.2
t
KLKH
±
0.2
t
KLKH
±
0.2
ns
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK79M72C164GB | MEMORY-SigmaRAM 16Meg 1x1z HSTL I/O (256K x 72) (27 pages 368K Rev. 7/6/01) |
| CXK79M72C165GB | MEMORY-SigmaRAM 16Meg 1x1z LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK79M72C164GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) |
| CXK79M72C165GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) |
| CXK79M72C165GB-4 | 制造商:SONY 功能描述: |
| CXK900L-S | 制造商:CHDS 功能描述:HEAT SINK 130x30x10mm |
| CX-L0612A | 制造商:KYOCERA Corporation 功能描述:INVERTER FOR 5.7" DISPLAYS |
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