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參數(shù)資料
| 型號： | CXK79M36C160GB |
| 英文描述： | MEMORY-SigmaRAM 16Meg 1x1 HSTL I/O (512K x 36) (27 pages 364K Rev. 7/6/01) |
| 中文描述： | 內(nèi)存SigmaRAM 16Meg 1x1 HSTL的I / O（為512k × 36）（27頁364K牧師7/6/01） |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 554K |
| 代理商： | CXK79M36C160GB |
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SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
5 / 30
July 19, 2002
Pin Description
Symbol
Type
Quantity
Description
A
Input
x72 = 16
x36 = 17
x18 = 18
Address Inputs - Registered on the rising edge of CK.
A1, A0
Input
2
Address Inputs 1,0 - Registered on the rising edge of CK. Initialize burst counter.
DQa, DQb
DQc, DQd
DQe, DQf
DQg, DQh
I/O
x72 = 72
x36 = 36
x18 = 18
Data Inputs / Outputs - Registered on the rising edge of CK during write operations.
Driven from the rising edge of CK during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
DQe - indicates Data Byte e
DQf - indicates Data Byte f
DQg - indicates Data Byte g
DQh - indicates Data Byte h
CK, CK
Input
2
Differential Input Clocks
CQ1, CQ1
CQ2, CQ2
Output
4
Output Clocks
E1
Input
1
Chip Enable Control Input - Registered on the rising edge of CK.
E1 = 0
enables the device to accept read and write commands.
E1 = 1
disables the device.
See the Clock Truth Table section for further information.
E2, E3
Input
2
Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See
the Clock Truth Table and Depth Expansion sections for further information.
EP2, EP3
Input
2
Programmable Chip Enable Active-Level Select Inputs - These pins must be tied
“high” or “l(fā)ow” at power-up. See the Clock Truth Table and Depth Expansion sec-
tions for further information.
ADV
Input
1
Address Advance Control Input - Registered on the rising edge of CK.
ADV = 0
loads a new address and begins a new operation when the device is
enabled.
ADV = 1
increments the address and continues the previous operation when the
device is enabled.
See the Clock Truth Table section for further information.
W
Input
1
Write Enable Control Input - Registered on the rising edge of CK.
W = 0
specifies a write operation when ADV = 0 and the device is enabled.
W = 1
specifies a read operation when ADV = 0 and the device is enabled.
See the Clock Truth Table section for further information.
Ba, Bb, Bc
Bd , Be, Bf
Bg, Bh
Input
x72 = 8
x36 = 4
x18 = 2
Byte Write Enable Control Inputs - Registered on the rising edge of CK.
Ba = 0
specifies write Data Byte a during a write operation
Bb = 0
specifies write Data Byte b during a write operation
Bc = 0
specifies write Data Byte c during a write operation
Bd = 0
specifies write Data Byte d during a write operation
Be = 0
specifies write Data Byte e during a write operation
Bf = 0
specifies write Data Byte f during a write operation
Bg = 0
specifies write Data Byte g during a write operation
Bh = 0
specifies write Data Byte h during a write operation
See the Clock Truth Table section for further information.
ZQ
Input
1
Output Impedance Control Resistor Input - This pin must be tied to V
SS
through an
external resistor RQ at power-up. Output driver impedance is set to one-fifth the
value of RQ, nominally. See the Output Driver Impedance Control section for further
information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK79M36C161GB | MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (512K x 36) (27 pages 364K Rev. 7/6/01) |
| CXK79M36C163GB | MEMORY-SigmaRAM 16Meg 1x2 LVCMOX I/O (512K x 36) (25 pages 360K Rev. 7/6/01) |
| CXK79M36C164GB | MEMORY-SigmaRAM 16Meg 1x1z HSTL I/O (512K x 36) (27 pages 368K Rev. 7/6/01) |
| CXK79M36C165GB | MEMORY-SigmaRAM 16Meg 1x1z LVCMOS I/O (512K x 36) (27 pages 364K Rev. 7/6/01) |
| CXK79M72C160GB | MEMORY-SigmaRAM 16Meg 1x1 HSTL I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK79M36C161GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (512K x 36) (27 pages 364K Rev. 7/6/01) |
| CXK79M36C162GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-33 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-4 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-5 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
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