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參數(shù)資料
| 型號： | CS5516-SD |
| 英文描述： | Analog-to-Digital Converter， 16-Bit |
| 中文描述： | 模擬到數(shù)字轉(zhuǎn)換器，16位 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 499K |
| 代理商： | CS5516-SD |
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CS5510/11/12/13
8
DS337F1
SWITCHING CHARACTERISTICS - CS5511/13
(T
A
= 25° C; V+ = 5 V ±5%; V- = 0 V; Input
Levels: Logic 0 = 0 V, Logic 1 = V+; C
L
= 50 pF)
Notes: 23.
The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is
retrieved from the serial port using the SCLK input pin.
The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being
read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10
percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is
entered after SCLK is logic 1 for t
SLP
time.
On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held
high (logic 1) for t
SLP
or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must
be held low (logic 0) for t
WAKE
or longer.
Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
24.
25.
26.
Parameter
Symbol
Min
Typ
Max
Unit
Internal Oscillator Timing
Internal Oscillator Frequency
Internal Oscillator Drift Over Temperature
Serial Port Timing
Serial Clock Frequency
SCLK High to Enter Sleep
SCLK Low to Exit Sleep
Rise Times
(Note 23)
f
osc
-
32
-
64
100
-
kHz
%/°C
-0.02
(Note 24)
SCLK
t
SLP
t
WAKE
t
rise
-
-
-
-
2
MHz
μs
μs
(Notes 24 and 25)
(Notes 24 and 25)
(Note 26)
200
10
2000
-
CSB
SCLK
SDO
-
-
-
-
-
50
1.0
10
-
μs
μs
ns
Fall Times
(Note 26)
CSB
SCLK
SDO
t
fall
-
-
-
-
-
50
-
-
1.0
10
-
-
-
μs
μs
ns
ns
ns
Serial Clock
Pulse Width High
Pulse Width Low
t
6
t
7
200
200
SDO Read Timing
CS
to Data Valid
SCLK Falling to New Data Bit
t
8
t
9
t
10
t
11
-
-
-
-
-
-
-
150
150
150
-
ns
ns
ns
ns
CS
Rising to SDO Hi-Z
CS
Falling to SCLK Rising
200
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相關(guān)代理商/技術(shù)參數(shù) |
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| CS5520-BP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Bridge Transducer ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5520-BS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Bridge Transducer ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5520-BSZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Bridge Transducer ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5520-BSZR | 制造商:Cirrus Logic 功能描述:Analog to Digital Converters - ADC 20-Bit Bridge Transducer ADC |
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