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參數(shù)資料
| 型號： | CS5516-SD |
| 英文描述： | Analog-to-Digital Converter， 16-Bit |
| 中文描述： | 模擬到數(shù)字轉(zhuǎn)換器，16位 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 499K |
| 代理商： | CS5516-SD |
CS5510/11/12/13
14
DS337F1
2.3.1
Digital Logic Levels
The many power supply configurations available in
the CS5510/11/12/13 allow for a wide range of dig-
ital logic levels. The logic high input and output
levels are determined by the V+ pin. The logic low
output on SDO is referenced to and driven by the
current logic-low voltage on CS. Since the
CS5510/11/12/13 do not include a dedicated
ground pin, CS
Low
defines the logic low level for
the digital interface. Figures 9 and 10 illustrate the
threshold levels of the CS5510/11/12/13 serial in-
terface (CS, SCLK, and SDO).
To accommodate opto-isolators, the SCLK input is
designed with a Schmitt-trigger to allow an opto-
isolator with slower rise and fall times to directly
drive the pin. Additionally, SDO is capable of sink-
ing up to 1 mA or sourcing up to 5 mA to directly
drive an opto-isolator LED. SDO will have less
than a 600 mV loss in the drive voltage when sink-
ing or sourcing its current. As shown in Figure 11,
the CS signal provides the sink current path for the
SDO pin when its voltage is low (i.e. the voltage
specified for SDO is relative to CS
Low
.).
2.4
The CS5510/12 and CS5511/13 provide distinct
modes for generating the master clock for the
ADCs. The CS5510/12 uses the SCLK input pin as
its operating clock. The CS5511/13 has an on-chip
oscillator that provides its master clock. The SCLK
pin on the CS5511/13 is used only to read data and
to put the part into sleep mode.
Clock Generator
2.4.1
External Clock Source for
CS5510/12
The user must provide an external (CMOS compat-
ible) clock to the CS5510/12. The clock is input to
SCLK where it is then divided down to provide the
master clock for the ADC. The output word rate
(OWR) for the CS5510/12 is derived from the
SCLK, and is equal to SCLK/612. Figure 12 illus-
trates an external 32.768 kHz (CMOS compatible)
clock oscillator that a user might consider.
Another clock generation option is to use a micro-
controller. Some microcontrollers have dedicated
timer/counter circuitry which can generate a clock
signal on an output pin with no software overhead.
Such a microcontroller circuit is shown in
Figure 13.
Figure 9. CS and SCLK Digital Input Levels.
V+
V-
V
V = 0.5 (
IL
- V-) + 0.6
V-
IH
LOW
- 0.45V
V+
=
CS
V +
V+
V+
V-
V
= V+ - 0.6V
V
V
IL
= CS
+ 0.6V
OH
OL
LOW
CS
LOW
Figure 10. SDO Digital Output Levels.
V+
Output Drive Logic
5 mA
1 mA
SDO (from SDO
Control Logic)
CS (to CS
Control Logic)
Max Source
Max Sink
Figure 11. Serial Port Output Drive Logic.
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