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參數(shù)資料
| 型號(hào)： | CS5516-SD |
| 英文描述： | Analog-to-Digital Converter， 16-Bit |
| 中文描述： | 模擬到數(shù)字轉(zhuǎn)換器，16位 |
| 文件頁(yè)數(shù)： | 7/26頁(yè) |
| 文件大小： | 499K |
| 代理商： | CS5516-SD |
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CS5510/11/12/13
DS337F1
7
SWITCHING CHARACTERISTICS - CS5510/12
(T
A
= 25° C; V+ = 5 V ±5%; V- = 0 V; Input
Levels: Logic 0 = 0 V, Logic 1 = V+; C
L
= 50 pF)
Notes: 20.
Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or
200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded
linearity specifications, as shown in Figures 14 and 15.
Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as
well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t
SLP
or longer,
the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t
WAKE
or
longer.
21.
22.
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Timing
Master Clock Frequency (CS5510)
Master Clock Frequency (CS5512)
Master Clock Duty Cycle
Rise Times
(Note 20)
(Note 20)
SCLK
SCLK
10
10
40
32.768
32.768
-
130
200
60
kHz
kHz
%
(Note 21)
CSB
SCLK
SDO
t
rise
-
-
-
-
-
50
1.0
10
-
μs
μs
ns
Fall Times
(Note 21)
CSB
SCLK
SDO
t
fall
-
-
-
-
-
50
1.0
10
-
μs
μs
ns
Serial Port Timing
Serial Clock Frequency (CS5510)
Serial Clock Frequency (CS5512)
SCLK High to Enter Sleep
SCLK Low to Exit Sleep
Serial Clock
(Note 22)
(Note 22)
(Note 22)
(Note 22)
SCLK
SCLK
t
SLP
t
WAKE
t
1
t
2
10
10
200
10
2
2
32.768
32.768
-
-
-
-
130
200
2000
-
60
60
kHz
kHz
μs
μs
μs
μs
Pulse Width High
Pulse Width Low
SDO Read Timing
CS
to Data Valid
SCLK Falling to New Data Bit
t
3
t
4
t
5
t
11
-
-
-
-
-
-
-
150
150
150
-
ns
ns
ns
ns
CS
Rising to SDO Hi-Z
CS
Falling to SCLK Rising
200
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