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參數(shù)資料
| 型號： | CS5132HGDWR24 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.5 A DUAL SWITCHING CONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, MS-013, SO-24 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 181K |
| 代理商： | CS5132HGDWR24 |
these large swings in gate-to-drain voltage tax the current
sourcing and sinking capabilities of the gate drive. In addi-
tion to charging and discharging CGS, the gate drive must
also supply the displacement current required by Cdg
(IGATE = Cdg dVdg/dt). Unless the gate-drive impedance is
very low, the VGS waveform commonly plateaus during
rapid changes in the drain-to-source voltage.
The most important aspect of FET performance is the Static
Drain-To-Source On-Resistance (RDSON), which effects
regulator efficiency and FET thermal management require-
ments. The On- Resistance determines the amount of cur-
rent a FET can handle without excessive power dissipation
that may cause overheating and potentially catastrophic
failure. As the drain current rises, especially above the con-
tinuous rating, the On-Resistance also increases. Its posi-
tive temperature coefficient is between +0.6%/C and
+0.85 %/C. The higher the On-Resistance the larger the
conduction loss is.
Both logic level and standard FETs can be used. The refer-
ence designs derive gate drive from the 12V supply which
is generally available in most computer systems and uti-
lizes logic level FETs. Multiple FETs may be paralleled to
reduce losses and improve efficiency and thermal manage-
ment.
Voltage applied to the FET gates depends on the applica-
tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail-to-rail due to overshoot caused by the capaci-
tive load they present to the controller IC.
We select Mitsubishi’s FS70VSJ-03 (D2 package):
30V withstand voltage; RDSON = 8m; ΘJA = 40°C/W;
Total Gate Charge = 50nC.
Step 6a: For the 2V Output Upper (Switching) FET
Calculate the 2V Output’s Maximum RMS Current through
the Switch:
IRMS(H) =
= 10.2A.
Calculate Switch Conduction Losses:
PRMS = IRMS2 × RDSON = 10.2A2 × 8m = 0.83W.
Calculate Switching Losses:
Switch On Losses:
PSW(ON) =
,
TRISE = 60ns,
(from Mitsubishi FS70VSJ-03 switching characteristics per-
formance curves):
T =
= 5s,
PSW(ON) =
= 0.16W.
Switch Off Losses:
PSW(OFF) =
,
TFALL = 160ns,
(from Mitsubishi FS70VSJ-03 switching characteristics per-
formance curves):
PSW(OFF) =
= 0.43W.
Upper FET Total Losses = Switching Conduction Losses +
Switch On Losses + Switch Off Losses:
PFETH(TOTAL) = 0.83W + 0.16W + 0.43W = 1.42W.
Calculate Maximum NFET Switch Junction Temperature:
TJ = TA + [(PFETH(TOTAL)) ×ΘJA ],
TJ = 50C + (1.412W) × 40°C/W = 107°C.
Calculate the Gate Driver Losses:
PGATE(H) = Q × VGATE × FSW
= 50nC
× 12V × 200KHz = 120mW.
Step 6b: Similar calculations apply for the 3.3V output.
Step 6c: Synchronous FET ( 2V Output)
Calculate Switch Conduction Losses:
PRMS = IRMS2 × RDSON = [IOUT2 × (1-D)] × RDSON
= [16A2
× 0.6] × 8m = 1.22W.
The synchronous MOSFET has no switching losses, except
for losses in the internal body diode, because it turns on
into near zero voltage conditions. The MOSFET body diode
will conduct during the non-overlap time and the resulting
power dissipation (neglecting reverse recovery losses) can
be calculated as follows:
PSW = VSD × ILOAD × non-overlap time
× switching frequency.
From the Mitsubishi FS70VSJ-03 source-drain diode for-
ward characteristics curve, VSD = 0.8V:
PSW = 0.8V × 16A × 65ns × 200kHz,
PSW = 0.16W.
5V
× 16A × 160 × 10-9
6
× 5 × 10-6
VIN × IOUT × TFALL
6T
5V
× 16A × 60× 10-9
1
FSW
(VIN × IOUT × TRISE)
6T
(IL(PEAK)2 + (IL(PEAK) × IL(VALLEY)) + IL(VALLEY2) × D
3
Application Information: continued
14
CS5132H
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