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參數(shù)資料
型號: CS4397-KSZ
廠商: Cirrus Logic Inc
文件頁數(shù): 8/34頁
文件大?。?/td> 0K
描述: IC DAC 24BIT MULTY STNDRD 28SOIC
標(biāo)準(zhǔn)包裝: 27
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): 192k
其它名稱: 598-1066-5
CS4397
16
DS333F1
3.0 REGISTER DESCRIPTION
3.1 DIFFERENTIAL DC OFFSET CALIBRATION
Mode Control Register (address 01h)
Access:
R/W in I2C and SPI.
Default:
0 - Disabled
Function:
Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be
automatically reset following completion of the calibration sequence.
3.2 SOFT MUTE
Mode Control Register (address 01h)
Access:
R/W in I2C and SPI.
Default:
0 - Enabled
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go low at the completion of the ramp period.
The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE.
76543
210
CAL
MUTE
M4
M3
M2
M1
M0
PDN
CAL
MODE
0
Disabled : CAL complete
1
Enabled : CAL initiated
Table 1.
76543
210
CAL
MUTE
M4
M3
M2
M1
M0
PDN
MUTE
MODE
0
Enabled
1
Disabled
Table 2.
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