參數(shù)資料
型號(hào): CS4397-KSZ
廠(chǎng)商: Cirrus Logic Inc
文件頁(yè)數(shù): 10/34頁(yè)
文件大?。?/td> 0K
描述: IC DAC 24BIT MULTY STNDRD 28SOIC
標(biāo)準(zhǔn)包裝: 27
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
輸出數(shù)目和類(lèi)型: 4 電壓,單極
采樣率(每秒): 192k
其它名稱(chēng): 598-1066-5
CS4397
18
DS333F1
4.0 PIN DESCRIPTION - PCM MODE
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal state machines registers are reset when low. When
high, the device will be in a normal operation mode .
Digital Ground - DGND
Pins 6 and 9, Inputs
Function:
Digital ground reference.
Digital Power - VD
Pins 7 and 8, Input
Function:
Digital power supply. Typically 5.0 to 3.0 VDC.
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Single
Speed Mode; either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x
128x or 192x the input sample rate in Quad Speed Mode. Tables 4-6 illustrate the standard audio sample
rates and the required master clock frequencies.
RST
DESCRIPTION
0
Enabled
1
Normal operation mode
1
2
3
4
5
6
7
8
9
10
11
12
5
1
2
6
28
27
26
25
24
23
22
21
20
19
18
17
13
14
16
15
Reset
RST
VREF
Voltage Reference
See Description
M4(AD0/CS)
FILT+
Reference Filter
See Description
M3(AD1/CDIN)
FILT-
Reference Ground
See Description
M2(SCL/CCLK)
CMOUT
Common ModeS Voltage
See Description M0(SDA/CDOUT)
AOUTL-
Differential Output
Digital Ground
DGND
AOUTL+
Differential Output
Digital Power
VD
VA
Analog Power
Digital Power
VD
AGND
Analog Ground
Digital Ground
DGND
AOUTR+
Differential Output
Master Clock
MCLK
AOUTR-
Differential Output
Serial Clock
SCLK
AGND
Analog Ground
Left/Right Clock
LRCK
MUTEC
Mute Control
Serial Data
SDATA
C/H
Control port/Hardware select
See Description
M1
MUTE
Soft Mute
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