參數(shù)資料
型號(hào): CS4397-KSZ
廠商: Cirrus Logic Inc
文件頁數(shù): 11/34頁
文件大小: 0K
描述: IC DAC 24BIT MULTY STNDRD 28SOIC
標(biāo)準(zhǔn)包裝: 27
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): 192k
其它名稱: 598-1066-5
CS4397
DS333F1
19
Serial Clock - SCLK
Pin 11, Input
Function:
Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right
clock, serial clock and serial data is defined by either the Mode Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in Figures 29-33
Left/Right Clock - LRCK
Pin 12, Input
Function:
The Left/Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 29-33
Serial Audio Data - SDATA
Pin 13, Input
Function:
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed inin Figures 29-33
Soft Mute - MUTE
Pin 15, Input
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
Sample Rate
(kHz)
MCLK (MHz)
256x
384x
512x
768x
32
8.1920
12.2880
16.3840
24.5760
44.1
11.2896
16.9344
22.5792
33.8688
48
12.2880
18.4320
24.5760
36.8640
Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x
192x
256x
384x
64
8.1920
12.2880
16.3840
24.5760
88.2
11.2896
16.9344
22.5792
33.8688
96
12.2880
18.4320
24.5760
36.8640
Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
64x
96x
128x
192x
176.4
11.2896
16.9344
22.5792
33.8688
192
12.2880
18.4320
24.5760
36.8640
Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
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