I2C Read To read from the device, follow the procedure" />
參數(shù)資料
型號: CS4392-KZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 7/40頁
文件大?。?/td> 0K
描述: IC DAC 24BIT 192KHZ W/VC 20TSSOP
標(biāo)準(zhǔn)包裝: 74
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 150mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): 200k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: CDB4392-ND - EVALUATION BOARD FOR CS4392
其它名稱: 598-1065-5
CS4392
DS459PP3
15
4.0.2b
I2C Read
To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.
1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits
must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of
the register pointed to by the MAP. The MAP register will contain the address of the last
register written to the MAP, or the default address (see section 4.1) if an I2C read is the first
operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue
an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired
registers are read, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is nec-
essary to initiate a STOP condition and follow the procedure detailed from steps 1 and 2
from the I2C Write instructions followed by step 1 of the I2C Read section. If no further
reads from other registers are desired, initiate a STOP condition to the bus.
SD A
SC L
001000
AD DR
AD 0
R/W
Sta rt
AC K
DA T A
1-8
AC K
DA T A
1-8
AC K
Stop
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
N o te 1
Figure 8. Control Port Timing, I2C Mode
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