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參數(shù)資料
| 型號： | CS4392-KZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 24BIT 192KHZ W/VC 20TSSOP |
| 標準包裝： | 74 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 150mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 200k |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 配用： | CDB4392-ND - EVALUATION BOARD FOR CS4392 |
| 其它名稱： | 598-1065-5 |
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CS4392
DS459PP3
23
6.5.2
Control Port Enable (Bit 5)
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-
up, the user should write 30h to register 5 within 10 ms following the release of Reset.
6.5.3
Power Down (Bit 4)
Function:
The device will enter a low-power state whenever this function is activated (set to 1). The power-down
bit defaults to ‘enabled’ (1) on power-up and must be disabled before normal operation will begin. The
contents of the control registers are retained when the device is in power-down.
6.5.4
AMUTEC = BMUTEC (Bit 3)
Function:
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
6.5.5
Freeze (Bit 2)
Function:
This function allows modifications to the control port registers without the changes taking effect until
Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously,
set the Freeze Bit, make all register changes, then Disable the Freeze bit.
6.5.6
Master Clock Divide (Bit 1)
Function:
This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in Tables 2 through 4 on page 10.
6.6
Mode Control 3 - Address 06h
6.6.1
Interpolation Filter Select (Bit 4)
Function:
This Function allows the user to select whether the Interpolation Filter has a fast (set to 0 - default) or
slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of
the roll of is greater for the ‘fast’ roll off filter.
B7
B6
B5
B4
B3
B2
B1
B0
Reserved
FILT_SEL
RMP_UP
RMP_DN
Reserved
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| CS4392-KZZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 114dB 192kHz Stereo DAC w/DSD RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4396 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz D/A Converter for Digital Audio |
| CS4396-KS | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24Bit 192 kHz DAC for Digital Audio RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4396-KSR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24Bit 192 kHz DAC for Digital Audio RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4396-KSZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 192 kHz DAC for Digital Audio RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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