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參數(shù)資料
| 型號(hào)： | CS4384-CQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8CH 103DB 192KHZ 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 520mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | 216k |
| 配用： | 598-1525-ND - BOARD EVAL FOR CS4384 DAC |
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36
DS620F1
CS4384
6.2.3
PCM/DSD Selection (DSD/PCM)
Default = 0
0 - PCM
1 - DSD
Function:
This function selects DSD or PCM Mode. The appropriate data and clocks should be present before
changing modes, or else MUTE should be selected.
6.2.4
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
Note:
When the device is configured in TDM Mode by setting DIF[3:0] to 1100 (see Digital Interface
Format (DIF)), this function is not available and these bits must be set to 0 for proper operation.
6.2.5
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
6.3
PCM Control (Address 03h)
6.3.1
Digital Interface Format (DIF)
Default = 0000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether
PCM or DSD Mode is selected.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 9-19.
Note:
While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
to ensure proper switching from one mode to another.
76
543
21
0
DIF3
DIF2
DIF1
DIF0
Reserved
FM1
FM0
00
000
01
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS4385-DQZR | IC DAC 8CH 114DB 192KHZ 48-LQFP |
| CS4391A-KZZR | IC DAC 24BIT 192KHZ W/VC 20TSSOP |
| CS4392-KZZ | IC DAC 24BIT 192KHZ W/VC 20TSSOP |
| CS4397-KSZ | IC DAC 24BIT MULTY STNDRD 28SOIC |
| CS4398-CZZ | IC DAC 120DB 192KHZ W/VC 28TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4384-DQZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 8-Channel D/A Converter |
| CS4384-DQZR | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 8-Channel D/A Converter |
| CS4385 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192kHz 8-CHANNEL D/A CONVERTER |
| CS4385_07 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter |
| CS4385_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter |
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