The CS4384 implements the channel mixing func" />
參數(shù)資料
型號(hào)： CS4384-CQZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 19/52頁
文件大?。?/td> 0K
描述： IC DAC 8CH 103DB 192KHZ 48-LQFP
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 520mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： 216k
配用： 598-1525-ND - BOARD EVAL FOR CS4384 DAC
26
DS620F1
CS4384
4.7
ATAPI Specification
The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 9 on page 43 and Figure 21 for additional informa-
tion.
4.8
Direct Stream Digital (DSD) Mode
In Software Mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The
DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The
first method uses a decimation free DSD processing technique which allows for features such as matched
PCM level output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data
directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features).
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data
input. In this mode the DSD_PM_Mode bit selects whether a 128Fs or 64x clock is used for phase modu-
lated 64x data (see Figure 22). Use of Phase Modulation Mode may not directly effect the performance of
the CS4384, but may lower the sensitivity to board level routing of the DSD data signals.
The CS4384 can detect errors in the DSD data which does not comply with the SACD specification. The
STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4384 to alter the incoming invalid DSD data.
Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the
MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).
More information for any of these register bits can be found in the “Parameter Definitions” on page 49.
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation
index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however,
performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital vol-
ume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There
is no need to change the volume control setting between PCM and DSD in order to have the 0 dB output
levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).
ΣΣ
A Channel
Volume
Control
Aout Ax
AoutBx
Left Channel
Audio Data
Right Channel
Audio Data
BChannel
Volume
Control
MUTE
SDINx
Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
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CS4384-DQZ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 8-Channel D/A Converter
CS4384-DQZR 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 8-Channel D/A Converter
CS4385 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192kHz 8-CHANNEL D/A CONVERTER
CS4385_07 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter
CS4385_08 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter
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