參數(shù)資料
型號： CS4382A-DQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 29/50頁
文件大?。?/td> 0K
描述： IC DAC 8CH 114DB 192KHZ 48-LQFP
標準包裝： 250
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 8
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 680mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 16 電壓，單極
采樣率（每秒）： 192k
配用： 598-1524-ND - BOARD EVAL FOR CS4382A DAC
DS618F2
35
CS4382A
DSD Mode:
The relationship between the oversampling ratio of the DSD audio data and the required
master clock-to-DSD-data-rate is defined by the Digital Interface Format pins.
6.3
Mode Control 3 (Address 03h)
6.3.1
Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change
will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently
monitored and implemented for each channel.
DIF2
DIF1
DIFO
DESCRIPTION
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
0
1
64x oversampled DSD data with a 6x MCLK to DSD data rate
0
1
0
64x oversampled DSD data with a 8x MCLK to DSD data rate
0
1
64x oversampled DSD data with a 12x MCLK to DSD data rate
1
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
1
0
1
128x oversampled DSD data with a 3x MCLK to DSD data rate
1
0
128x oversampled DSD data with a 4x MCLK to DSD data rate
1
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Digital Interface Formats - DSD Mode
7
6
5
432
10
SZC1
SZC0
SNGLVOL
RMP_UP
MUTEC+/-
AMUTE
Reserved
MUTEC
1
0
001
00
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