參數資料
| 型號： | CS4382A-DQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數： | 14/50頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8CH 114DB 192KHZ 48-LQFP |
| 標準包裝： | 250 |
| 位數： | 24 |
| 數據接口： | 串行 |
| 轉換器數目： | 8 |
| 電壓電源： | 模擬和數字 |
| 功率耗散（最大）： | 680mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數目和類型： | 16 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 配用： | 598-1524-ND - BOARD EVAL FOR CS4382A DAC |
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DS618F2
21
CS4382A
4. APPLICATIONS
The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,
44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input
via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software
Mode through IC or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
4.2
Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in Figure 6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “Digital
Speed Mode
(sample-rate range)
Sample
Rate
(kHz)
MCLK (MHz)
Software
Mode Only
MCLK Ratio
256x
384x
512x
768x
1024x*
Single-Speed
(4 to 50 kHz)
32
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
MCLK Ratio
128x
192x
256x
384x
512x*
Double-Speed
(50 to 100 kHz)
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
MCLK Ratio
64x
96x
128x
192x
256x*
Quad-Speed
(100 to 200 kHz)
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Note:
These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CS4382A-DQZR | 功能描述:音頻數/模轉換器 IC IC 114dB 192 kHz 8Chn DAC w/DSD supt. RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| CS4382A-EQZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-channel D/A Converter |
| CS4382A-EQZR | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-channel D/A Converter |
| CS4382-KQZ | 功能描述:數模轉換器- DAC IC 114dB 24-bit 102kHz 8Ch DAC RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4382-KQZR | 功能描述:數模轉換器- DAC IC 114dB 24-bit 102kHz 8Ch DAC RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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