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| 型號： | CS42L52-DNZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 消費(fèi)家電 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, MO-220, QFN-40 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 1800K |
| 代理商： | CS42L52-DNZR |
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DS680F1
27
CS42L52
5/13/08
4.2.1
MIC Inputs
The input pins 21, 22, 23, and 24 accept stereo line-level or microphone signals. For microphone inputs,
either single-ended or differential configuration is allowed, providing programmable pre-amplification of
low-level signals. In the single-ended configuration, an internal MUX chooses one of two stereo sets (se-
lection is made independently on channels A and B). In the differential configuration, an internal voltage
follower cascaded with the pre-amplifier maintains high input impedance and provides noise rejection
above the MICxGAIN setting. The pre-amps are biased to VQ in both configurations.
4.2.2
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum (MAX) threshold settings, and responds by applying attenuation as neces-
sary to maintain the resulting level below the MAX threshold. To apply this attenuation, the ALC first low-
ers the PGA gain settings and then increases the digital attenuation levels. All attenuation is applied at a
programmable attack rate.
When input signal levels fall below the minimum (MIN) threshold, the ALC responds by removing any at-
tenuation that it has previously applied until all ALC-applied attenuation has been removed or until the
MAX threshold is again crossed. To remove this attenuation, the ALC first decreases the digital attenua-
tion levels and then increases the PGA gain. All attenuation is removed at a programmable release rate.
It should be noted that the ALC is applied independently to channels A and B with one exception: the input
signals on both channels A and B must be below the MIN threshold in order for the ALC attenuation to be
released on channel B.
Attack and release rates are affected by the ADC soft-ramp/zero-cross settings and sample rate, Fs. ALC
soft-ramp and zero-cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers.
Notes:
1.
When ALC x is enabled and the PGAxVOL[5:0] is set above 12 dB, the ADCxVOL[7:0] should not be
set below 0 dB.
2.
The maximum realized gain must be set in the PGAxVOL register. The ALC will only apply the gain
set in the PGAxVOL.
3.
The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level
Referenced Control
Register Location
MICxCFG ............................
PDN_MICx ..........................
MICxGAIN ...........................
MIC1-
-
+
-
+
MIC1+
MIC2-
-
+
-
+
MIC2+
23
21
24
22
MICACFG=’1'b
MICBCFG=’1'b
MICAGAIN[4:0]
MICBGAIN[4:0]
16..32 dB/
1 dB steps
16..32 dB/
1 dB steps
PDN_MICA=’0'b
PDN_MICB=’0'b
to summing
PGA A
Note: Output to PGA = (MIC
+ - MIC-)*gain + MIC-
to summing
PGA B
MIC1A
-
+
MIC2A
MIC1B
-
+
MIC2B
23
21
24
22
MICACFG=’0'b
MICBCFG=’0'b
MICAGAIN[4:0]
MICBGAIN[4:0]
16..32 dB/
1 dB steps
16..32 dB/
1 dB steps
PDN_MICA=’0'b
PDN_MICB=’0'b
MICASEL
MICBSEL
to summing
PGA A
to summing
PGA B
VQ
Figure 6. Single-Ended MIC Configuration
Figure 7. Differential MIC Configuration
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