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| 型號： | CPPM00WP100 |
| 元件分類： | 網(wǎng)絡(luò)處理器 |
| 英文描述： | Network Processor Programming Models: The Key to Achieving Faster Time-To-Market and Extending Product Life |
| 中文描述： | 網(wǎng)絡(luò)處理器編程模型：關(guān)鍵實現(xiàn)更快地向市場和延長產(chǎn)品壽命 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 363K |
| 代理商： | CPPM00WP100 |
May 2, 2001
Making Programming More Simple Through a “Communications” API
5
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The fundamental building blocks of the C-5 NP are the 16
embedded Channel Processors (CPs). Each CP consists of a
dedicated RISC CPU and dual Serial Data Processors (SDPs).
The CP structure combines the best attributes of specialized
configurable state-machine architectures with a fully program-
mable RISC core. CPs can be assigned to physical interfaces,
aggregated together to support higher-bandwidth I/O streams,
or assigned internally as a dedicated internal coprocessor.
The SDPs handle data encoding/decoding, framing, formatting,
parsing, error checking (CRCs), and data movement. The SDPs
also control programmable external pin logic, allowing them to
implement virtually any layer 1 interface including connection to
T/E-Carrier framers, 10/100 Ethernet PHY (RMII), Gigabit
Ethernet PHY (GMII or TBI), OC-3 PHY, OC-12 PHY, and OC-48
framers/PHY. At layer 2, the SDPs can be independently config-
ured to support Ethernet, PoS, HDLC streams, ATM, Frame
Relay, FibreChannel, or virtually any format including various
encapsulations such as MPLS. The programmability of the
SDPs support the diversity of media access control interfaces,
as well as first-order parsing requirements, and can support the
“mix-and-match” requirements of different implementations on
a port-by-port basis. This efficiently supports the needs of
various interworking applications.
The SDPs are programmed in microcode, which is provided by
C-Port for the vast majority of applications (all flavors of
Ethernet, IP and ATM over SONET, T/E carrier serial data
streams, and so on). All the tools necessary for equipment
vendors to program the SDPs (including assembler and simu-
lator support) are available. Support for MAC level diversity is
available without any user coding.
The CP’s RISC core, programmed in C or C++, is available to
focus on higher-level tasks such as final switching / forwarding
decision making, scheduling, statistics gathering, or other tasks
required for higher-level services. The RISC core in each CP
operates at the core clock rate of the C-5 NP has dedicated
internal instruction and data memory, and implements an
industry standard instruction subset, avoiding the issues asso-
ciated with proprietary instructions. With the SDPs off-loading
the “bit level” tasks from the RISC core, the capacity of the
RISC machine can be dedicated to the tasks that benefit the
most from high-level language implementations.
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The C-5 NP also provides five coprocessors optimized for
common tasks and used by the CPs. These coprocessors
handle shared tasks including table lookup, queue manage-
ment, buffer management, fabric interfacing, and supervisory
processing. Each unit is highly configurable and offers perfor-
mance and capabilities that, if packaged as stand-alone devices,
would be considered best-in-class communications compo-
nents. For example, the Table Lookup Unit (TLU) enables a wide
range of traffic classification functions and supports multiple,
different search algorithms.
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The CPs, supported by the coprocessors, provide the funda-
mental building blocks from which multiple applications can be
supported through high-level programming. For example, the
CPs can take on different personalities to support ATM,
Ethernet/IP PPP/IP Frame Relay, Channelized HDLC, or even
proprietary protocols through a combination of microcode in
the SDPs and C/C++ code running on the RISC core. The data
paths through the CPs can be configured for external connec-
tion (to PHYs) or looped back internally, for use as an applica-
tions “coprocessor”
Although there are 16 CPs per C-5 NP each CP is independently
programmable, avoiding the limitations typical of traditional
symmetric multiprocessor designs. With the flexibility provided
by the CP architectures, it is a straight forward task to write
software for the CP to perform a given function.
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Hardware flexibility is usually accompanied with complexity
driven by the number of possible functional permutations. By
adapting the concept of standard Application Programming
Interfaces (APIs) to communications processing, this
complexity can be put at the service of the programmer. The
C-5 NP supports C-Ware Application Programming Interfaces
(APIs), a set of open, efficient interfaces that abstract common
functions from the underlying hardware. See Figure 4.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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