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| 型號： | CPPM00WP100 |
| 元件分類： | 網絡處理器 |
| 英文描述： | Network Processor Programming Models: The Key to Achieving Faster Time-To-Market and Extending Product Life |
| 中文描述： | 網絡處理器編程模型：關鍵實現(xiàn)更快地向市場和延長產品壽命 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 363K |
| 代理商： | CPPM00WP100 |
May 2, 2001
Network Processor Programming Model Choices
3
Today, each of these functions presents the challenge of a wide
diversity of possible implementations, rapid evolution based on
continuing innovation, strong interdependencies between func-
tions, and a need for interworking between the diverse proto-
cols. Delivering programmability and integration of these
functions represents a major evolution in network device
design.
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The computing world has always debated about what is the
best processor hardware architectures: CISC versus RISC,
single CPU versus multi-CPU, coprocessors versus faster
clocks, and so on. However, it is the softwarethat determines
the success of computing platforms, both in terms of perfor-
mance and programming ease. The limited success of
symmetric, parallel computing architectures proved that raw
computing power was not the decisive factor, but rather how
that power could be harnessed by software The same is true
for network processors — the decisive factor is how the
programming model serves the platform requirements of fast,
simple, and flexible programmability.
There are two primary metrics for evaluating network processor
programming models. The first is the level of programmability
offered, both in terms of which functions can be programmed
(see Figure 2), as well as the extent that these various func-
tions can be programmed. While the physical space, cost, and
power benefits of high functional integration into a single
processor is well understood, there is a forgotten benefit to the
programming model. Processor architectures that assume a
“bag of parts” approach provide programmability for a subset
of the forwarding plane functions, limiting the ability of
programmers to effectively deal with the diversity within each
level and the often complex interactions between them. Like-
wise, providing appropriate programmability within each level is
crucial to accommodating these interactions. Hence a fully inte-
grated, fully programmable network processor architecture is a
major prerequisite for an effective programming model.
The second, and most important metric, is the actual program-
ming method for the processor. Perhaps the largest struggle in
traditional network system design with ASICs has been a
“hardware first” architectural mentality, with software engi-
neers designing around a less-than-ideal hardware/software
partitioning. Network processor programming models need to
turn this around, providing a hardware processor platform that
serves the requirements of the software functions and, in the
end, the software designers themselves. The key criteria is a
simple programming paradigm, using well known methods,
without sacrificing product performance.
The network processors available today fall into three broad
categories of programming methods, with a spectrum of capa-
bilities within each. These categories are discussed below.
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These devices implement virtually all the forwarding plane func-
tions in custom designed, low-level microcode machines. All
tasks including data parsing, search algorithms, data transfor-
mation, queuing, and scheduling algorithms must be specifi-
cally programmed by the designer. These machines maximize
performance through multi-threading, which generally requires
the microcode writer to consider everything from memory
access times to thread interactions when optimizing each func-
tion.
Also, these architectures implement multiple instances (typi-
cally 6 to12) of these machines in parallel, with fixed hardware
schedulers assigning incoming data to a given machine based
on availability. This is similar to traditional symmetric multipro-
cessing computing models, which places additional constraints
on the microcode writer to assure proper interactions and
ordering of forwarded data.
Microcode’s strength lies in the efficiency of the code once it is
written. The code can be compact and fast. However, the
downside of programming in low level microcode, compre-
hending everything from memory access latencies to multipro-
cessing dependencies, is the lack of portability of these code
designs to other products based on same processor and to
new, faster versions or new generations of processors. This
code tends to be “one time use” which when combined with
the inherent difficulty of writing microcode, might make these
processors suitable for point product designs, but seriously
compromises the value of “software programmability” for an
overall communications platform.
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Another programming model focuses on leveraging proprietary
search and pattern-matching algorithms to the communications
processing task, specifically for parsing and classification. A
number of these algorithms use custom “fourth generation
languages” (4GLs) to describe the parsing and
pattern-matching requirements for a number of applications.
These 4GLs provide a concise method of “programming” the
classification function, and processors that implement these
algorithms provide a partial solution to this piece of the commu-
nications processing task.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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