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參數(shù)資料
| 型號： | CPPM00WP100 |
| 元件分類： | 網(wǎng)絡(luò)處理器 |
| 英文描述： | Network Processor Programming Models: The Key to Achieving Faster Time-To-Market and Extending Product Life |
| 中文描述： | 網(wǎng)絡(luò)處理器編程模型：關(guān)鍵實現(xiàn)更快地向市場和延長產(chǎn)品壽命 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 363K |
| 代理商： | CPPM00WP100 |
4
The algorithms implemented by these processors typically
trade-off memory size for search speed, which may or may not
be an issue for the system design. There are, however, larger
impacts on the programming model against the two main
criteria outlined above. First, these processors focus almost
exclusively on the parsing and classification tasks, providing
only one piece of a “bag of parts” solution. The designer must
either build the required external hardware (and associated soft-
ware) around this part, or, if available, use other piece parts
provided by the processor vendor (sometimes configurable
with microcode as described above). In either case, the
programming domain is disjoint, compromising what functions
are actually programmable and the depth of that programma-
bility.
Even if the other functions are ignored, using a proprietary
description language for the classification requires new skills
and tools, not just for the coding tasks but for debug, analysis,
and maintenance. Good tools can mitigate some of this cost,
but the inconsistency between the other forwarding plane func-
tions and the control plane functions will remain.
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The “standard language” programming model leverages
existing languages (such as C and C++ with their inherent
benefits such as readily available skilled programmers and
industry standard programming tools), usually combined with
special coprocessors, to implement the various communica-
tions processing tasks. These use multiple embedded RISC
cores as a key processing element to support the execution of
standard C/C++ programs imple-
menting the desired behavior.
Note that the use of RISC cores in a
network processor does not auto-
matically mean that the processor
was designed to support a
higher-level programming language
paradigm. Many “RISC-based”
network processors implement
proprietary instruction sets (or
proprietary extensions), which,
while expedient from a hardware
design perspective, force program-
mers to write all or significant
portions of their code in RISC
assembly language. Similarly, the
processing capacity may not be
adequate to support reasonable
implementations in a higher-level
language. Thus, programming
these processors can be just as
complex as writing in low-level
microcode.
To effectively support the requirements of a communications
platform, the programming model must support the ability to
write effective programs in a higher-level standard language.
The means the RISC cores need to have enough horsepower
within a rich coprocessing architecture to support an API
abstraction layer that insulates the operating code from low
level chip implementation details without sacrificing perfor-
mance. This is the key to providing a simple programming
model environment and extending the life of the software.
The implementation of the coprocessing architecture is critical,
as the coprocessors must off-load the RISC processor from the
communications tasks that are notoriously poor in standard
CPUs (such as the bit manipulation typically required in parsing
and data transformation tasks).
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C-Port’s C-5 Network Processor (NP) is an example of a
network processor designed from the ground up to provide a
simple and robust programming model. The C-5 NP provides
complete programmability for each of the forwarding plane
tasks using standard C/C++ programming, enabling universal
applications in a wide variety of network devices. The C-5 NP
combines multiple RISC cores, specialized coprocessors, and
microcode engines within a single integrated circuit to offer a
full range of programmability at high performance. Figure 3
shows a block diagram of the C-5 NP
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C-5 NP Software-optimized Architecture
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
Buses (60Gpbs Bandwidth)
Cluster
Cluster
CP-1
CP-0
CP-2
CP-3
CP-12 CP-13 CP-14 CP-15
External
Host CPU
(optional)
OC-3
PHY Interface Examples:
10/100 Ethernet
OC-12
OC-48
Gigabit Ethernet
External
PROM
(optional)
Control
Logic
(optional)
Fabric
Processor Boundary
Buffer
Mgmt
Unit
Channel
Processors
SDRAM
C-5
NP
SRAM
SRAM
Table
Lookup
Unit
Fabric
Processor
Executive Processor
Queue
Mgmt
Unit
PCI
Serial
PROM
Channel Processor
32-bit
RISC
Core
DSerial
DSerial
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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