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參數(shù)資料
| 型號： | COPCH912C |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 275K |
| 代理商： | COPCH912C |
COP912C/COP912CH Pinout
Pin Description
V
CC
and
GND
are the power supply pins.
CKI
is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
RESET
is the master reset input. See Reset description.
PORT L
is an 8-bit I/O port.
There are two registers associated to configure the L port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
Port L
Config.
0
0
1
1
Three data memory address locations are allocated for this
port, one each for data register [00D0], configuration register
[00D1] and the input pins [00D2].
PORT G
is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7).
All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated to configure the G port: a
data register and a configuration register. Therefore each G
port bit can be individually configured under software control
as shown below:
Port L
Data
0
1
0
1
PORT L
Setup
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Port G
Config.
0
0
1
1
Three data memory address locations are allocated for this
port, one for data register [00D4], one for configuration reg-
ister [00D5] and one for the input pins [00D6]. Since G6 and
Port G
Data
0
1
0
1
PORT G
Setup
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
G7 are Hi-Z input only pins, any attempt by the user to con-
figure them as outputs by writing a one to the configuration
register will be disregarded. Reading the G6 and G7 configu-
ration bits will return zeroes. Note that the chip will be placed
in the Halt mode by writing a “1” to the G7 data bit.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock op-
tion is R/C- or external clock)
Pins G1 and G2 currently do not have any alternate func-
tions.
The selection of alternate Port G functions are done through
registers PSW [00EF] to enable external interrupt and
CNTRL [00EE] to select TIO and MICROWIRE operations.
Functional Description
The internal architecture is shown in the block diagram. Data
paths are illustrated in simplified form to depict how the vari-
ous logic elements communicate with each other in imple-
menting the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or shift
operations in one cycle time. There are five CPU registers:
A
is the 8-bit Accumulator register
PC is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B
is the 8-bit address register and can be auto incre-
mented or decremented
X
is the 8-bit alternate address register and can be auto
incremented or decremented.
20 DIP
DS012060-3
Top View
Order Number COP912C-XXX/N,
COP912CH-XXX/N
20 SO Wide
DS012060-4
Top View
Order Number COP912C-XXX/WM,
COP912CH-XXX/WM
FIGURE 2. COP912C/COP912CH Pinout
C
www.national.com
6
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