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參數(shù)資料
| 型號： | COPCH912C |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 275K |
| 代理商： | COPCH912C |
Timer/Counter
(Continued)
Table 4 below details the TIMER modes of operation and
their associated interrupts. Bit 4 of CNTRL is used to start
and stop the timer/counter. Bits 5, 6 and 7 of the CNTRL reg-
ister select the timer modes. The ENTI (Enable Timer Inter-
rupt) and TPND (Timer Interrupt Pending) bits in the PSW
register are used to control the timer interrupts.
Care must be taken when reading from and writing to the
timer and its associated autoreload/capture register. The
timer and autoreload/capture register are both 16-bit, but
they are read from and written to one byte at a time. It is rec-
ommended that the timer be stopped before writing a new
value into it. The timer may be read “on the fly” without stop-
ping it if suitable precautions are taken. One method of read-
ing the timer “on the fly” is to read the upper byte of the timer
first, and then read the lower byte. If the most significant bit
of the lower byte is then tested and found to be high, then the
upper byte of the timer should be read again and this new
value used.
TABLE 4. Timer Modes and Control Bits
CNTRL Bits
6
0
0
1
1
0
0
1
1
Operation Mode
Timer
Interrupt
Timer
Counts On
7
0
0
0
0
1
1
1
1
5
0
1
0
1
0
1
0
1
External Event Counter with Autoreload Register
External Event Counter with Autoreload Register
Not Allowed
Not Allowed
Timer with Autoreload Register
Timer with Autoreload Register and Toggle TIO Out
Timer with Capture Register
Timer with Capture Register
Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TIO Positive Edge
TIO Negative Edge
TIO Positive Edge
TIO Negative Edge
Not Allowed
Not Allowed
tc
tc
tc
tc
TIMER APPLICATION EXAMPLE
The timer has an autoreload register that allows any fre-
quency to be programmed in the timer PWM mode. The
timer underflow can be programmed to toggle output bit G3,
and may also be programmed to generate a timer interrupt.
Consequently, a fully programmable PWM output may be
easily generated.
The timer counts down and when it underflows, the value
from the autoreload register is copied into the timer. The
CNTRL register is programmed to both toggle the G3 output
and generate a timer interrupt when the timer underflows.
Following each timer interrupt, the user’s program alternately
loads the values of the “on” time and the “off” time into the
timer
autoreload
register.
pulse-width-modulated (PWM) output waveform is gener-
ated to a resolution of one instruction cycle time. This PWM
application example is shown in Figure 10
Consequently,
a
Interrupts
There are three interrupt sources:
1.
A maskable interrupt on external G0 input positive or
negative edge sensitive under software control
2.
A maskable interrupt on timer underflow or timer capture
3.
Anon-maskable software/error interrupt on opcode zero.
The GIE (global interrupt enable) bit enables the inter-
rupt function. This is used in conjunction with ENI and
ENTI to select one or both of the interrupt sources. This
bit is reset when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupt respec-
tively. Thus the user can select either or both sources to in-
terrupt the microcontroller when GIE is enabled. IEDG se-
DS012060-12
FIGURE 9. Timer in Input Capture Mode
DS012060-13
FIGURE 10. Timer Based PWM Application
C
www.national.com
10
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