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參數(shù)資料
| 型號： | COPCH912C |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 275K |
| 代理商： | COPCH912C |
Addressing Modes
(Continued)
This addressing mode issued with the LD B,
#
instruction,
where the immediate
#
is less than 16. The instruction con-
tains a 4-bit immediate field as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction with the instruction
field being added to the program counter to produce the next
instruction address. JP has a range from 31 to +32 to allow
a one byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “blocks” or “pages” when using JP
since all 15 bits of the PC are used.
Absolute
This mode is used with the JMP and JSR instructions with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion in the entire 32k program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serves as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A
B
X
SP
S
PC
PU
PL
C
HC
GIE
8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
8-Bit Data Segment Address Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1-Bit of PSW Register for Carry
1-Bit of PSW Register for Half Carry
1-Bit of PSW Register for Global Interrupt Enable
Symbols
[B]
[X]
MD
Mem
MemI
Imm
Reg
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
Direct Addressed Memory, or B
Direct Addressed Memory, B, or Immediate Data
8-Bit Immediate Data
Register Memory: Addresses F0 to FF
(Includes B, X, and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
Bit
←
TABLE 7. Instruction Set
Instr
Function
Register Operation
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
X
LD
LD
LD
X
X
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
#
Reg
#
, Mem
#
, Mem
#
, Mem
A, Mem
A, MemI
Mem, Imm
Reg, Imm
A, [B
±
]
A, [X
±
]
Add
Add with Carry
Subtract with Carry
Logical AND
Logical OR
Logical Exclusive-OR
IF Equal
IF Greater than
IF B not Equal
Decrement Reg, Skip if Zero
Set Bit
Reset Bit
If Bit
Exchange A with Memory
Load A with Memory
Load Direct Memory Immed.
Load Register Memory Immed.
Exchange A with Memory [B]
Exchange A with Memory [X]
A
←
A + MemI
A
←
A + MemI + C, C
←
Carry
A
←
A MemI + C, C
←
Carry
A
←
A and MemI
A
←
A or MemI
A
←
A xor MemI
Compare A and MemI, Do Next if A = MemI
Compare A and MemI, Do Next if A
>
MemI
Do Next If Lower 4 Bits of B not = Imm
Reg
←
Reg - 1, Skip if Reg Goes to Zero
1 to Mem.Bit (Bit = 0 to 7 Immediate)
0 to Mem.Bit (Bit = 0 to 7 Immediate)
If Mem.Bit is True, Do Next Instruction
A
Mem
A
←
MemI
Mem
←
Imm
Reg
←
Imm
A
[B] (B
←
B
±
1)
A
[X] (X
←
X
±
1)
C
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13
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