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參數(shù)資料
| 型號： | COPCH912C |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 275K |
| 代理商： | COPCH912C |
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE control register contains the fol-
lowing bits:
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 = 2, 01 = 4, 1x = 8)
IEDG
External interrupt edge polarity select
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
TRUN
Used to start and stop the timer/counter
(1 = run, 0 = stop)
TC1
Timer Mode Control Bit
TC2
Timer Mode Control Bit
TC3
Timer Mode Control Bit
7
TC1
0
TC2
TC3
TRUN
MSEL
IEDG
SL1
SL0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)
ENI
External interrupt enable
BUSY MICROWIRE busy shifting flag
IPND
External interrupt pending
ENTI
Timer interrupt enable
TPND Timer interrupt pending
(timer underflow or capture edge)
C
Carry Flip/flop
HC
Half carry Flip/flop
7
HC
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-
struction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C and
RESET C will set and clear both the carry flags. Table 5 lists
out the instructions that effect the HC and the C flags.
0
C
TPND
ENTI
IPND
BUSY
ENI
GIE
TABLE 5. Instructions Effecting HC and C Flags
Instr.
ADC
SUBC
SETC
RESET
C
RRC
HC Flag
C Flag
Depends on Operands
Depends on Operands
Set
Set
Depends on Operands
Depends on Operands
Set
Set
Depends on Operands
Depends on Operands
MEMORY MAP
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
TABLE 6. Memory Map
Address
00 to 2F
Contents
On-chip RAM Bytes (48 Bytes)
Address
30 to 7F
Contents
Unused RAM Address Space (Reads as all
ones)
Expansion Space for On-Chip EERAM
(Reads Undefined Data)
Port L Data Register
Port L Configuration Register
Port L Input Pins (read only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (read only)
Reserved
Reserved
Reserved
On-Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE Shift Register
Timer Lower Byte
Timer Upper Byte
Timer Autoreload Register Lower Byte
Timer Autoreload Register Upper Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
(16 Bytes)
X Register
SP Register
B Register
Reading other unused memory locations will return unde-
fined data.
80 to BF
C0 to CF
D0
D1
D2
D3
D4
D5
D6
D7
D8 to DB
DC to DF
E0 to EF
E0 to E7
E8
E9
EA
EB
EC
ED
EE
EF
F0 to FF
FC
FD
FE
Addressing Modes
The device has ten addressing modes, six for operand ad-
dressing and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode for the chip. The oper-
and is the data memory addressed by the
B
or
X
pointer.
Register Indirect With Auto Post Increment Or Decre-
ment
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the
B
or
X
pointer. This is a register indirect mode that automati-
cally post increments or post decrements the
B
or
X
pointer
after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the oper-
and.
Short Immediate
C
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