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參數(shù)資料
| 型號： | COP8SCR9 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲器的帶32K存儲器，虛擬EEPROM和電壓過低復(fù)位的微控制器) |
| 中文描述： | 8位CMOS閃存為基礎(chǔ)的32K的內(nèi)存，虛擬EEPROM和欠壓（8位基于的CMOS閃速存儲器的帶32K的存儲器，微控制器虛擬的EEPROM和電壓過低復(fù)位的微控制器） |
| 文件頁數(shù)： | 32/68頁 |
| 文件大小： | 714K |
| 代理商： | COP8SCR9 |
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7.0 Power Saving Features
(Continued)
IDLE mode. The NOP’s are placed either at the beginning of
the IDLE Timer interrupt routine or immediately following the
“enter IDLE mode” instruction.
For more information on the IDLE Timer and its associated
interrupt, see the description in the Timers section.
7.4 DUAL CLOCK MODE OPERATION
This mode of operation allows for high speed operation of
the Core clock and low speed operation of the Idle Timer.
This mode can be entered from either the High Speed mode
or the Low Speed mode.
To enter from the High Speed mode, the following sequence
must be followed:
1.
Software sets the LSON bit to 1.
2.
Software waits until the low speed oscillator has stabi-
lized. See Table 4
3.
Software sets the DCEN bit to 1.
To enter from the Low Speed mode, the following sequence
must be followed:
1.
Software sets the HSON bit to 1.
2.
Software waits until the high speed oscillator has stabi-
lized. See Table 4, Startup Times.
3.
Software clears the CCKSEL bit to 0.
7.4.1 Dual Clock HALT Mode
The fully static architecture of this device allows the state of
the microcontroller to be frozen. This is accomplished by
stopping the high speed clock of the device during the HALT
mode. The processor can be forced to exit the HALT mode
and resume normal operation at any time. The low speed
clock remains on during HALT in the Dual Clock mode.
During normal operation, the actual power consumption de-
pends heavily on the clock speed and operating voltage
used in an application and is shown in the Electrical Speci-
fications. In the HALT mode, the device only draws a small
leakage current, plus current for the BOR feature (if en-
abled), plus the 32 kHz oscillator current, plus any current
necessary for driving the outputs. Since total power con-
sumption is affected by the amount of current required to
drive the outputs, all I/Os should be configured to draw
minimal current prior to entering the HALT mode, if possible.
Entering The Dual Clock Halt Mode
The device enters the HALT mode under software control
when the Port G data register bit 7 is set to 1. All processor
action stops in the middle of the next instruction cycle, and
power consumption is reduced to a very low level. In order to
expedite exit from HALT, the low speed oscillator is left
running when the device is Halted in the Dual Clock mode.
However, the Idle Timer will not be clocked.
Exiting The Dual Clock Halt Mode
When the HALT mode is entered by setting bit 7 of the Port
G data register, there is a choice of methods for exiting the
HALT mode: a chip Reset using the RESET pin or a Multi-
Input Wakeup. The Reset method and Multi-Input Wakeup
method can be used with any clock option.
HALT Exit Using Reset
A device Reset, which is invoked by a low-level signal on the
RESET input pin, takes the device out of the Dual Clock
mode and puts it into the High Speed mode.
HALT Exit Using Multi-Input Wakeup
The device can be brought out of the HALT mode by a
transition received on one of the available Wakeup pins. The
pins used and the types of transitions sensed on the Multi-
input pins are software programmable. For information on
programming and using the Multi-Input Wakeup feature, re-
fer to 7.6 MULTI-INPUT WAKEUP
A start-up delay is required between the device wakeup and
the execution of program instructions. The start-up delay is
mandatory, and is implemented whether or not the CLKDLY
bit is set. This is because all crystal oscillators and resona-
tors require some time to reach a stable frequency and full
operating amplitude.
If the start-up delay is used, the IDLE Timer (Timer T0)
provides a fixed delay from the time the clock is enabled to
the time the program execution begins. Upon exit from the
HALT mode, the IDLE Timer is enabled with a starting value
of 256 and is decremented with each instruction cycle using
the high speed clock. (The instruction clock runs at one-fifth
the frequency of the high speed oscillatory.) An internal
Schmitt trigger connected to the on-chip CKI inverter en-
sures that the IDLE Timer is clocked only when the high
speed oscillator has a large enough amplitude. (The Schmitt
trigger is not part of the oscillator closed loop.) When the
IDLE Timer underflows, the clock signals are enabled on the
chip, allowing program execution to proceed. Thus, the delay
is equal to 256 instruction cycles. After exiting HALT, the Idle
Timer will return to being clocked by the low speed clock.
Note:
To ensure accurate operation upon start-up of the
device using Multi-input Wakeup, the instruction in the appli-
cation program used for entering the HALT mode should be
followed by two consecutive NOP (no-operation) instruc-
tions.
Options
This device has two options associated with the HALT mode.
The first option enables the HALT mode feature, while the
second option disables HALT mode operation. Selecting the
disable HALT mode option will cause the microcontroller to
ignore any attempts to HALT the device under software
control. See 4.5 OPTION REGISTERfor more details on this
option bit.
7.4.2 Dual Clock Idle Mode
In the IDLE mode, program execution stops and power
consumption is reduced to a very low level as with the HALT
mode. However, both oscillators, IDLE Timer (Timer T0), and
Clock Monitor continue to operate, allowing real time to be
maintained. The Idle Timer is clocked by the low speed
clock. The device remains idle for a selected amount of time
up to 1 second, and then automatically exits the IDLE mode
and returns to normal program execution using the high
speed clock.
The device is placed in the IDLE mode under software
control by setting the IDLE bit (bit 6 of the Port G data
register).
The IDLE Timer window is selectable from one of five values,
0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second and
2 seconds. Selection of this value is made through the ITMR
register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to
keep track of elapsed time in the IDLE state. The IDLE Timer
runs continuously at the low speed clock rate, whether or not
the device is in the IDLE mode. Each time the bit of the timer
associated with the selected window toggles, the T0PND bit
C
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