參數(shù)資料
型號(hào)： COP8SCR9
廠商： National Semiconductor Corporation
英文描述： 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲(chǔ)器的帶32K存儲(chǔ)器，虛擬EEPROM和電壓過(guò)低復(fù)位的微控制器)
中文描述： 8位CMOS閃存為基礎(chǔ)的32K的內(nèi)存，虛擬EEPROM和欠壓（8位基于的CMOS閃速存儲(chǔ)器的帶32K的存儲(chǔ)器，微控制器虛擬的EEPROM和電壓過(guò)低復(fù)位的微控制器）
文件頁(yè)數(shù)： 30/68頁(yè)
文件大?。?/td> 714K
代理商： COP8SCR9
7.0 Power Saving Features
(Continued)
Core clock will be the low speed clock. Before
switching this bit to either state, the appropriate
clock should be turned on and stabilized.
DCEN
0
CCKSEL
0
High Speed Mode. Core and Idle
Timer Clock = High Speed
Dual Clock Mode. Core clock = High
Speed; Idle Timer = Low Speed
Low Speed Mode. Core and Idle
Timer Clock = Low Speed
Invalid. If this is detected, the Low
Speed Mode will be forced.
This bit is reserved and must be 0.
Bits 2–0:
These are bits used to control the Idle Timer. See
6.1 TIMER T0 (IDLE TIMER) for the description
of these bits.
Table 17 lists the valid contents for the four most significant
bits of the ITMR Register. Any other value is illegal and will
result in an unrecoverable loss of a clock to the CPU core. To
prevent this condition, the device will automatically reset if
any illegal value is detected.
1
0
1
1
0
1
RSVD:
TABLE 17. Valid Contents of Dual Clock Control Bits
LSON HSON DCEN CCKSEL
0
1
1
1
Mode
0
0
0
0
High Speed
High Speed/Dual Clock
Transition
Dual Clock
Dual Clock/Low Speed
Transition
Low Speed
1
1
1
1
1
1
0
1
1
0
1
1
This internal reset presets the Idle Timer to 00Fx which
results in an internal reset of 240 to 256 t
. This delay is
independent of oscillator type and the state of BOR enable.
7.2 OSCILLATOR STABILIZATION
Both the high speed oscillator and low speed oscillator have
a startup delay associated with them. When switching be-
tween the modes, the software must ensure that the appro-
priate oscillator is started up and stabilized before switching
to the new mode. See Table 4, Startup Times for startup
times for both oscillators.
7.3 HIGH SPEED MODE OPERATION
This mode of operation allows high speed operation for both
the main Core clock and also for the Idle Timer. This is the
default mode of the device and will always be entered upon
any of the Reset conditions described in the Reset section. It
can also be entered from Dual Clock mode. It cannot be
directly entered from the Low Speed mode without passing
through the Dual Clock mode first.
To enter from the Dual Clock mode, the following sequence
must be followed using two separate instructions:
1.
Software clears DCEN to 0.
2.
Software clears LSON to 0.
7.3.1 High Speed Halt Mode
The fully static architecture of this device allows the state of
the microcontroller to be frozen. This is accomplished by
stopping the internal clock of the device during the HALT
mode. The controller also stops the CKI pin from oscillating
during the HALT mode. The processor can be forced to exit
the HALT mode and resume normal operation at any time.
During normal operation, the actual power consumption de-
pends heavily on the clock speed and operating voltage
used in an application and is shown in the Electrical Speci-
fications. In the HALT mode, the device only draws a small
leakage current, plus current for the BOR feature (if en-
abled), plus any current necessary for driving the outputs.
Since total power consumption is affected by the amount of
current required to drive the outputs, all I/Os should be
configured to draw minimal current prior to entering the
HALT mode, if possible. In order to reduce power consump-
tion even further, the power supply (V
) can be reduced to
a very low level during the HALT mode, just high enough to
guarantee retention of data stored in RAM. The allowed
lower voltage level (V
R
) is specified in the Electrical Specs
section.
Entering The High Speed Halt Mode
The device enters the HALT mode under software control
when the Port G data register bit 7 is set to 1. All processor
action stops in the middle of the next instruction cycle, and
power consumption is reduced to a very low level.
Exiting The High Speed Halt Mode
There is a choice of methods for exiting the HALT mode: a
chip Reset using the RESET pin or a Multi-Input Walk-up.
HALT Exit Using Reset
A device Reset, which is invoked by a low-level signal on the
RESET input pin, takes the device out of the HALT mode
and starts execution from address 0000H. The initialization
software should determine what special action is needed, if
any, upon start-up of the device from HALT. The initialization
of all registers following a RESET exit from HALT is de-
scribed in the Reset section of this manual.
HALT Exit Using Multi-Input Walk-up
The device can be brought out of the HALT mode by a
transition received on one of the available Walk-up pins. The
pins used and the types of transitions sensed on the Multi-
input pins are software programmable. For information on
programming and using the Multi-Input Wake-up feature,
refer to the Multi-Input Wake-up section.
A start-up delay is required between the device wakeup and
the execution of program instructions, depending on the type
of chip clock. The start-up delay is mandatory, and is imple-
mented whether or not the CLKDLY bit is set. This is be-
cause all crystal oscillators and resonators require some
time to reach a stable frequency and full operating ampli-
tude.
The IDLE Timer (Timer T0) provides a fixed delay from the
time the clock is enabled to the time the program execution
begins. Upon exit from the HALT mode, the IDLE Timer is
enabled with a starting value of 256 and is decremented with
each instruction cycle. (The instruction clock runs at one-fifth
the frequency of the high speed oscillator.) An internal
Schmitt trigger connected to the on-chip CKI inverter en-
sures that the IDLE Timer is clocked only when the oscillator
has a large enough amplitude. (The Schmitt trigger is not
part of the oscillator closed loop.) When the IDLE Timer
C
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