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參數(shù)資料
| 型號(hào)： | COP8SCR9 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲(chǔ)器的帶32K存儲(chǔ)器，虛擬EEPROM和電壓過低復(fù)位的微控制器) |
| 中文描述： | 8位CMOS閃存為基礎(chǔ)的32K的內(nèi)存，虛擬EEPROM和欠壓（8位基于的CMOS閃速存儲(chǔ)器的帶32K的存儲(chǔ)器，微控制器虛擬的EEPROM和電壓過低復(fù)位的微控制器） |
| 文件頁數(shù)： | 21/68頁 |
| 文件大?。?/td> | 714K |
| 代理商： | COP8SCR9 |
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5.0 In-System Programming
(Continued)
5.4 MANEUVERING BACK AND FORTH BETWEEN
FLASH MEMORY AND BOOT ROM
When using ISP, at some point, it will be necessary to
maneuver between the flash program memory and the
Boot ROM, even when using customized ISP routines.
This is because it’s not possible to execute from the flash
program memory while it’s being programmed.
Two instructions are available to perform the jumping back
and forth: Jump to Boot (JSRB) and Return to Flash
(RETF). The JSRB instruction is used to jump from flash
memory to Boot ROM, and the RETF is used to return
from the Boot ROM back to the flash program memory.
See 13.0 Instruction Set for specific details on the opera-
tion of these instructions.
The JSRB instruction must be used in conjunction with the
Key register. This is to prevent jumping to the Boot ROM
in the event of run-away software. For the JSRB instruc-
tion to actually jump to the Boot ROM, the Key bit must be
set. This is done by writing the value shown in Table 10 to
the Key register. The Key is a 6 bit key and if the key
matches, the KEY bit will be set for 8 instruction cycles.
The JSRB instruction must be executed while the KEY bit
is set. If the KEY does not match, then the KEY bit will not
be set and the JSRB will jump to the specified location in
the flash memory. In emulation mode, if a breakpoint is
encountered while the KEY is set, the counter that counts
the instruction cycles will be frozen until the breakpoint
condition is cleared. The Key register is a memory
mapped register. Its format when writing is shown in Table
10 In normal operation, it is not necessary to test the KEY
bit before using the JSRB instruction. The additional in-
structions required to test the key may cause the key to
time-out before the JSRB can be executed.
TABLE 10. KEY Register Write Format
KEY When Writing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
1
1
0
X
X
Bits 7–2:
Key value that must be written to set the KEY bit.
Bits 1–0:
Don’t care.
5.5 FORCED EXECUTION FROM BOOT ROM
When the user is developing a customized ISP routine, code
lockups due to software errors may be encountered. There is
a hardware method to get out of these lockups and force
execution from the Boot ROM MICROWIRE/PLUS routine,
so that the customer can erase the Flash Memory code and
start over. The method to force this condition is to drive the
G6 pin to high voltage (2X V
) and activate Reset. The high
voltage condition on G6 must be held for at least 3 instruc-
tion cycles longer than Reset is active. This special condition
will start execution from location 0000 in the Boot ROM
where the user can input the appropriate commands, using
MICROWIRE/PLUS, to erase the flash program memory and
reprogram it.
While the G6 pin is at high voltage, the Load Clock will be
output onto G5, which will look like an SK clock to the
MICROWIRE/PLUS routine executing in slave mode. How-
ever, when G6 is at high voltage, the G6 input will also look
like a logic 1. The MICROWIRE/PLUS routine in Boot ROM
monitors the G6 input, waits for it to go low, debounces it,
and then enables the ISP routine. CAUTION: The Load clock
on G5 could be in conflict with the user’s external SK. It is up
to the user to resolve this conflict, as this condition is con-
sidered a minor issue that’s only encountered during soft-
ware development.
The user should also be cautious of
the high voltage applied to the G6 pin. This high voltage
could damage other circuitry connected to the G6 pin
(e.g. the parallel port of a PC).
The user may wish to
disconnect other circuitry while G6 is connected to the high
voltage.
5.6 RETURN TO FLASH MEMORY WITHOUT
HARDWARE RESET
After programming the entire program memory, including
options, it is necessary to exit the Boot ROM and return to
the flash program memory for program execution. Upon
receipt and completion of the EXIT command through the
MICROWIRE/PLUS ISP, the ISP code will reset the part and
begin execution from the flash program memory as de-
scribed in the Reset section. This assumes that the FLEX bit
in the Option register was programmed to 1.
5.7 MICROWIRE/PLUS ISP
National Semiconductor provides a program, which is avail-
able from our web site at www.national.com/cop8, that is
capable of programming a device from the parallel port of a
PC. The software accepts manually input commands and is
capable of downloading standard Intel HEX Format files.
Users who wish to write their own MICROWIRE/PLUS ISP
host software should refer to the COP8 FLASH ISP User
Manual, available from the same web site. This document
includes details of command format and delays necessary
between command bytes.
The MICROWIRE/PLUS ISP supports the following features
and commands:
Write a value to the ISP Write Timing Register. NOTE:
This
must
be
the
first
MICROWIRE/PLUS ISP mode.
Erase the entire flash program memory (mass erase).
Erase a page at a specified address.
Read Option register.
Read a byte from a specified address.
Write a byte to a specified address.
Read multiple bytes starting at a specified address.
Write multiple bytes starting at a specified address.
Exit ISP and return execution to flash program memory.
The following table lists the MICROWIRE/PLUS ISP com-
mands and provides information on required parameters and
return values.
command
after
entering
C
www.national.com
21
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