參數(shù)資料
型號: COP8SBR9
廠商: National Semiconductor Corporation
英文描述: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲器的帶32K存儲器,虛擬EEPROM和電壓過低復位的微控制器)
中文描述: 8位CMOS閃存為基礎的32K的內(nèi)存,虛擬EEPROM和欠壓(8位基于的CMOS閃速存儲器的帶32K的存儲器,微控制器虛擬的EEPROM和電壓過低復位的微控制器)
文件頁數(shù): 51/68頁
文件大?。?/td> 714K
代理商: COP8SBR9
11.0 MICROWIRE/PLUS
MICROWIRE/PLUS is a serial SPI compatible synchronous
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with MICROWIRE/PLUS
or SPI peripherals (i.e. A/D converters, display drivers,
EEPROMs etc.) and with other microcontrollers which sup-
port the MICROWIRE/PLUS or SPI interface. It consists of
an 8-bit serial shift register (SIO) with serial data input (SI),
serial data output (SO) and serial shift clock (SK). Figure 28
shows a block diagram of the MICROWIRE/PLUS logic.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
arrangement with the internal clock source is called the
Master
mode
of
operation.
MICROWIRE/PLUS arrangement with an external shift clock
is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table 24 details the
different clock rates that may be selected.
Similarly,
operating
the
TABLE 24. MICROWIRE/PLUS
Master Mode Clock Select
SL1
0
0
1
SL0
0
1
x
SK Period
2 x t
C
4 x t
C
8 x t
C
Where t
C
is the instruction cycle clock
11.1 MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 28shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
Warning:
The SIO register should only be loaded when the SK clock is
in the idle phase. Loading the SIO register while the SK clock
is in the active phase, will result in undefined data in the SIO
register.
Setting the BUSY flag when the input SK clock is in the
active phase while in the MICROWIRE/PLUS is in the slave
mode may cause the current SK clock for the SIO shift
register to be narrow. For safety, the BUSY flag should only
be set when the input SK clock is in the idle phase.
11.1.1 MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. The MSEL
bit in the CNTRL register must be set to enable the SO and
SK functions onto the G Port. The SO and SK pins must also
be selected as outputs by setting appropriate bits in the Port
G configuration register. In the slave mode, the shift clock
stops after 8 clock pulses. Table 25 summarizes the bit
settings required for Master mode of operation.
11.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 25 summarizes the settings required to enter
the Slave mode of operation.
TABLE 25. MICROWIRE/PLUS Mode Settings
This table assumes that the control flag MSEL is set.
G4 (SO)
Config. Bit
1
G5 (SK)
Config. Bit
1
G4
Fun.
SO
G5
Fun.
Int.
SK
Int.
SK
Ext.
SK
Ext.
SK
Operation
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Slave
MICROWIRE/PLUS
Slave
0
1
TRI-
STATE
SO
1
0
0
0
TRI-
STATE
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
C
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