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參數資料
| 型號： | COP8SBR9 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲器的帶32K存儲器，虛擬EEPROM和電壓過低復位的微控制器) |
| 中文描述： | 8位CMOS閃存為基礎的32K的內存，虛擬EEPROM和欠壓（8位基于的CMOS閃速存儲器的帶32K的存儲器，微控制器虛擬的EEPROM和電壓過低復位的微控制器） |
| 文件頁數： | 15/68頁 |
| 文件大?。?/td> | 714K |
| 代理商： | COP8SBR9 |
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4.0 Functional Description
(Continued)
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Moni-
tor bit set. The WATCHDOG and Clock Monitor circuits
are inhibited during reset. The WATCHDOG service win-
dow bits being initialized high default to the maximum
WATCHDOG service window of 64k T0 clock cycles. The
Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached
the minimum specified frequency at the termination of
reset. A Clock Monitor error will cause an active low error
output on pin G1. This error output will continue until
16–32 T0 clock cycles following the clock frequency
reaching the minimum specified value, at which time the
G1 output will go high.
4.7.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up ini-
tialization, the user must ensure that the RESET pin of a
device without the Brownout Reset feature is held low until
the device is within the specified V
CC
voltage. An R/C circuit
on the RESET pin with a delay 5 times (5x) greater than the
power supply rise time is recommended. Reset should also
be wide enough to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this device is shown in
Figure 9
4.7.2 On-Chip Brownout Reset
When enabled, the device generates an internal reset as
V
rises. While V
is less than the specified brownout
voltage (V
), the device is held in the reset condition and
the Idle Timer is preset with 00Fx (240–256 t
). When V
reaches a value greater than V
, the Idle Timer starts
counting down. Upon underflow of the Idle Timer, the internal
reset is released and the device will start executing instruc-
tions. This internal reset will perform the same functions as
external reset. Once V
is above the V
and this initial Idle
Timer time-out takes place, instruction execution begins and
the Idle Timer can be used normally. If, however, V
drops
below the selected V
, an internal reset is generated, and
the Idle Timer is preset with 00Fx. The device now waits until
V
CC
is greater than V
bor
and the countdown starts over.
When enabled, the functional operation of the device is
guaranteed down to the V
bor
level.
One exception to the above is that the brownout circuit will
insert a delay of approximately 3 ms on power up or any time
the V
drops below a voltage of about 1.8V. The device will
be held in Reset for the duration of this delay before the Idle
Timer starts counting the 240 to 256 t
. This delay starts as
soon as the V
rises above the trigger voltage (approxi-
mately 1.8V). This behavior is shown in Figure 10
DS101389-12
FIGURE 9. Reset Circuit Using External Reset
DS101389-13
FIGURE 10. Brownout Reset Operation
C
www.national.com
15
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| COP8SBR9HVA8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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