參數(shù)資料
型號(hào): COP8SAB7SLB9
廠商: National Semiconductor
文件頁(yè)數(shù): 43/62頁(yè)
文件大小: 0K
描述: IC MCU OTP 8BIT 2K 28LAMINATECSP
標(biāo)準(zhǔn)包裝: 1
系列: COP8™ 8SA
核心處理器: COP8
芯體尺寸: 8-位
速度: 10MHz
連通性: Microwire/Plus(SPI)
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲(chǔ)器容量: 2KB(2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-VFQFN,CSP
包裝: 剪切帶 (CT)
其它名稱: *COP8SAB7SLB9
COP8SAB7SLB9CT
13.8
Opcode
Table
Upper
Nibble
F
E
D
C
B
A
9
876
5
4
3
2
1
0
LowerNibble
JP15
JP31
LD
0F0,
#i
DRSZ
0F0
RRCA
RC
ADC
A,#i
ADC
A,[B]
IFBIT
0,[B]
ANDSZ
A,
#i
LD
B,#0F
IFBNE
0
JSR
x000
x0FF
JMP
x000
x0FF
JP+17
INTR
0
JP14
JP30
LD
0F1,
#i
DRSZ
0F1
*
S
C
SUBC
A,
#i
SUBC
A,[B]
IFBIT
1,[B]
*L
D
B,#0E
IFBNE
1
JSR
x100
x1FF
JMP
x100
x1FF
JP+18
JP+2
1
JP13
JP29
LD
0F2,
#i
DRSZ
0F2
X
A,[X+]
X
A,[B+]
IFEQ
A,#i
IFEQ
A,[B]
IFBIT
2,[B]
*L
D
B,#0D
IFBNE
2
JSR
x200
x2FF
JMP
x200
x2FF
JP+19
JP+3
2
JP12
JP28
LD
0F3,
#i
DRSZ
0F3
X
A,[X]
X
A,[B]
IFGT
A,#i
IFGT
A,[B]
IFBIT
3,[B]
*L
D
B,#0C
IFBNE
3
JSR
x300
x3FF
JMP
x300
x3FF
JP+20
JP+4
3
JP11
JP27
LD
0F4,
#i
DRSZ
0F4
VIS
LAID
ADD
A,#i
ADD
A,[B]
IFBIT
4,[B]
CLRA
LD
B,#0B
IFBNE
4
JSR
x400
x4FF
JMP
x400
x4FF
JP+21
JP+5
4
JP10
JP26
LD
0F5,
#i
DRSZ
0F5
RPND
JID
AND
A,#i
AND
A,[B]
IFBIT
5,[B]
SWAPA
LD
B,#0A
IFBNE
5
JSR
x500
x5FF
JMP
x500
x5FF
JP+22
JP+6
5
JP9
JP25
LD
0F6,
#i
DRSZ
0F6
X
A,[X]
X
A,[B]
XOR
A,#i
XOR
A,[B]
IFBIT
6,[B]
DCORA
LD
B,#09
IFBNE
6
JSR
x600
x6FF
JMP
x600
x6FF
JP+23
JP+7
6
JP8
JP24
LD
0F7,
#i
DRSZ
0F7
*
OR
A,#i
OR
A,[B]
IFBIT
7,[B]
PUSHA
LD
B,#08
IFBNE
7
JSR
x700
x7FF
JMP
x700
x7FF
JP+24
JP+8
7
JP7
JP23
LD
0F8,
#i
DRSZ
0F8
NOP
RLCA
LD
A,#i
IFC
SBIT
0,[B]
RBIT
0,[B]
LD
B,#07
IFBNE
8
JSR
x800
x8FF
JMP
x800
x8FF
JP+25
JP+9
8
JP6
JP22
LD
0F9,
#i
DRSZ
0F9
IFNE
A,[B]
IFEQ
Md,#i
IFNE
A,#i
IFNC
SBIT
1,[B]
RBIT
1,[B]
LD
B,#06
IFBNE
9
JSR
x900
x9FF
JMP
x900
x9FF
JP+26
JP+10
9
JP5
JP21
LD
0FA,
#i
DRSZ
0FA
LD
A,[X+]
LD
A,[B+]
LD
[B+],#i
INCA
SBIT
2,[B]
RBIT
2,[B]
LD
B,#05
IFBNE
0A
JSR
xA00
xAFF
JMP
xA00
xAFF
JP+27
JP+11
A
JP4
JP20
LD
0FB,
#i
DRSZ
0FB
LD
A,[X]
LD
A,[B]
LD
[B],#i
DECA
SBIT
3,[B]
RBIT
3,[B]
LD
B,#04
IFBNE
0B
JSR
xB00
xBFF
JMP
xB00
xBFF
JP+28
JP+12
B
JP3
JP19
LD
0FC,
#i
DRSZ
0FC
LD
Md,#i
JMPL
X
A,Md
POPA
SBIT
4,[B]
RBIT
4,[B]
LD
B,#03
IFBNE
0C
JSR
xC00
xCFF
JMP
xC00
xCFF
JP+29
JP+13
C
JP2
JP18
LD
0FD,
#i
DRSZ
0FD
DIR
JSRL
LD
A,Md
RETSK
SBIT
5,[B]
RBIT
5,[B]
LD
B,#02
IFBNE
0D
JSR
xD00
xDFF
JMP
xD00
xDFF
JP+30
JP+14
D
JP1
JP17
LD
0FE,
#i
DRSZ
0FE
LD
A,[X]
LD
A,[B]
LD
[B],#i
RET
SBIT
6,[B]
RBIT
6,[B]
LD
B,#01
IFBNE
0E
JSR
xE00
xEFF
JMP
xE00
xEFF
JP+31
JP+15
E
JP0
JP16
LD
0FF,
#i
DRSZ
0FF
*
LD
B,#i
RETI
SBIT
7,[B]
RBIT
7,[B]
LD
B,#00
IFBNE
0F
JSR
xF00
xFFF
JMP
xF00
xFFF
JP+32
JP+16
F
Where,
i
is
the
immediate
data
Md
is
a
directly
addressed
memory
location
*
is
a
n
unused
opcode
The
opcode
60
Hex
is
also
the
opcode
for
IFBIT
#i,A
COP8SA
Family
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