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| 型號： | COP8SAB7SLB9 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 4/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 8BIT 2K 28LAMINATECSP |
| 標準包裝： | 1 |
| 系列： | COP8™ 8SA |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 10MHz |
| 連通性： | Microwire/Plus（SPI） |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 2KB（2K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 28-VFQFN，CSP |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | *COP8SAB7SLB9 COP8SAB7SLB9CT |
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AC Electrical Characteristics (Continued)
40C
≤ T
A ≤ +85C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Inputs
t
SETUP
4.5V
≤ V
CC ≤ 5.5V
200
ns
2.7V
≤ V
CC < 4.5V
500
ns
t
HOLD
4.5V
≤ V
CC ≤ 5.5V
60
ns
2.7V
≤ V
CC < 4.5V
150
ns
Output Propagation Delay (Note 16)
R
L = 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK
4.5V
≤ V
CC ≤ 5.5V
0.7
s
2.7V
≤ V
CC < 4.5V
1.75
s
All Others
4.5V
≤ V
CC ≤ 5.5V
1.0
s
2.7V
≤ V
CC < 4.5V
2.5
s
MICROWIRE Setup Time (t
UWS) (Note 16)
20
ns
MICROWIRE Hold Time (t
UWH) (Note 16)
56
ns
MICROWIRE Output Propagation Delay (t
UPD)
220
ns
MICROWIRE Maximum Shift Clock
Master Mode
500
kHz
Slave Mode
1
MHz
Input Pulse Width (Note 17)
Interrupt Input High Time
1
t
C
Interrupt Input Low Time
1
t
C
Timer 1 Input High Time
1
t
C
Timer 1 Input Low Time
1
t
C
Reset Pulse Width
1
s
Note 11: tC = Instruction cycle time (Clock input frequency divided by 10).
Note 12: Maximum rate of voltage change must be < 0.5 V/ms.
Note 13: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180 out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 14: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G Port data register.
Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC
when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These
two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.
Note 18: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
DS012838-9
FIGURE 4. MICROWIRE/PLUS Timing
COP8SA
Family
www.national.com
11
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