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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | COP8SAB7SLB9 |
| 寤犲晢锛� | National Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/62闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 8BIT 2K 28LAMINATECSP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | COP8™ 8SA |
| 鏍稿績铏曠悊鍣細 | COP8 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 閫ｉ€氭€э細 | Microwire/Plus锛圫PI锛� |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 2KB锛�2K x 8锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 28-VFQFN锛孋SP |
| 鍖呰锛� | 鍓垏甯� (CT) |
| 鍏跺畠鍚嶇ū锛� | *COP8SAB7SLB9 COP8SAB7SLB9CT |
绗�1闋�绗�2闋�绗�3闋�鐣�(d膩ng)鍓嶇4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�
AC Electrical Characteristics (Continued)
40C
鈮� T
A 鈮� +85C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Inputs
t
SETUP
4.5V
鈮� V
CC 鈮� 5.5V
200
ns
2.7V
鈮� V
CC < 4.5V
500
ns
t
HOLD
4.5V
鈮� V
CC 鈮� 5.5V
60
ns
2.7V
鈮� V
CC < 4.5V
150
ns
Output Propagation Delay (Note 16)
R
L = 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK
4.5V
鈮� V
CC 鈮� 5.5V
0.7
s
2.7V
鈮� V
CC < 4.5V
1.75
s
All Others
4.5V
鈮� V
CC 鈮� 5.5V
1.0
s
2.7V
鈮� V
CC < 4.5V
2.5
s
MICROWIRE Setup Time (t
UWS) (Note 16)
20
ns
MICROWIRE Hold Time (t
UWH) (Note 16)
56
ns
MICROWIRE Output Propagation Delay (t
UPD)
220
ns
MICROWIRE Maximum Shift Clock
Master Mode
500
kHz
Slave Mode
1
MHz
Input Pulse Width (Note 17)
Interrupt Input High Time
1
t
C
Interrupt Input Low Time
1
t
C
Timer 1 Input High Time
1
t
C
Timer 1 Input Low Time
1
t
C
Reset Pulse Width
1
s
Note 11: tC = Instruction cycle time (Clock input frequency divided by 10).
Note 12: Maximum rate of voltage change must be < 0.5 V/ms.
Note 13: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180 out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 14: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2鈥揋5
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G Port data register.
Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC
when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These
two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.
Note 18: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
DS012838-9
FIGURE 4. MICROWIRE/PLUS Timing
COP8SA
Family
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| COP8SAC720M8 | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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