9.0 Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector l" />
參數(shù)資料
型號： COP8SAB7SLB9
廠商： National Semiconductor
文件頁數(shù)： 24/62頁
文件大?。?/td> 0K
描述： IC MCU OTP 8BIT 2K 28LAMINATECSP
標(biāo)準(zhǔn)包裝： 1
系列： COP8™ 8SA
核心處理器： COP8
芯體尺寸： 8-位
速度： 10MHz
連通性： Microwire/Plus（SPI）
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 24
程序存儲器容量： 2KB（2K x 8）
程序存儲器類型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-VFQFN，CSP
包裝： 剪切帶 (CT)
其它名稱： *COP8SAB7SLB9
COP8SAB7SLB9CT
9.0 Interrupts (Continued)
ample, if the Software Trap routine is located at 0310 Hex,
then the vector location 0yFE and -0yFF should contain the
data 03 and 10 Hex, respectively. When a Software Trap
interrupt occurs and the VIS instruction is executed, the
program jumps to the address specified in the vector table.
The interrupt sources in the vector table are listed in order of
rank, from highest to lowest priority. If two or more enabled
and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
from the interrupt service routine, the next highest-level
pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are en-
abled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in
the vector table. This is an unusual occurrence, and may be
the result of an error. It can legitimately result from a change
in the enable bits or pending flags prior to the execution of
the VIS instruction, such as executing a single cycle instruc-
tion which clears an enable flag at the same time that the
pending flag is set. It can also result, however, from inad-
vertent execution of the VIS command outside of the context
of an interrupt.
The default VIS interrupt vector can be useful for applica-
tions in which time critical interrupts can occur during the
servicing of another interrupt. Rather than restoring the pro-
gram context (A, B, X, etc.) and executing the RETI instruc-
tion, an interrupt service routine can be terminated by return-
ing to the VIS instruction. In this case, interrupts will be
serviced in turn until no further interrupts are pending and
the default VIS routine is started. After testing the GIE bit to
ensure that execution is not erroneous, the routine should
restore the program context and execute the RETI to return
to the interrupted program.
This technique can save up to fifty instruction cycles (t
c), or
more, (50 s at 10 MHz oscillator) of latency for pending
interrupts with a penalty of fewer than ten instruction cycles
if no further interrupts are pending.
To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Al-
though it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The
use of polling allows the standard arbitration ranking to be
altered, but the reliability of the interrupt system is compro-
mised. The polling routine must individually test the enable
and pending bits of each maskable interrupt. If a Software
Trap interrupt should occur, it will be serviced last, even
though it should have the highest priority. Under certain
conditions, a Software Trap could be triggered but not ser-
viced, resulting in an inadvertent “l(fā)ocking out” of all
maskable interrupts by the Software Trap pending flag.
Problems such as this can be avoided by using VIS
instruction.
TABLE 5. Interrupt Vector Table
Arbitration
Vector (Note 20)
Ranking
Source
Description
Address
(Hi-Low Byte)
(1) Highest
Software
INTR Instruction
0yFE–0yFF
(2)
Reserved
Future
0yFC–0yFD
(3)
External
G0
0yFA–0yFB
(4)
Timer T0
Underflow
0yF8–0yF9
(5)
Timer T1
T1A/Underflow
0yF6–0yF7
(6)
Timer T1
T1B
0yF4–0yF5
(7)
MICROWIRE/PLUS
BUSY Low
0yF2–0yF3
(8)
Reserved
Future
0yF0–0yF1
(9)
Reserved
Future
0yEE–0yEF
(10)
Reserved
Future
0yEC–0yED
(11)
Reserved
Future
0yEA–0yEB
(12)
Reserved
Future
0yE8–0yE9
(13)
Reserved
Future
0yE6–0yE7
(14)
Reserved
Future
0yE4–0yE5
(15)
Port L/Wakeup
Port L Edge
0yE2–0yE3
(16) Lowest
Default
VIS Instruction
0yE0–0yE1
Execution without any interrupts
Note 20: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last
address of a block. In this case, the table must be in the next block.
COP8SA
Family
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