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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | COP8SAB7SLB9 |
| 寤犲晢锛� | National Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/62闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 8BIT 2K 28LAMINATECSP |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | COP8™ 8SA |
| 鏍稿績铏曠悊鍣細 | COP8 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 閫ｉ€氭€э細 | Microwire/Plus锛圫PI锛� |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 2KB锛�2K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 28-VFQFN锛孋SP |
| 鍖呰锛� | 鍓垏甯� (CT) |
| 鍏跺畠鍚嶇ū锛� | *COP8SAB7SLB9 COP8SAB7SLB9CT |
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9.0 Interrupts (Continued)
ample, if the Software Trap routine is located at 0310 Hex,
then the vector location 0yFE and -0yFF should contain the
data 03 and 10 Hex, respectively. When a Software Trap
interrupt occurs and the VIS instruction is executed, the
program jumps to the address specified in the vector table.
The interrupt sources in the vector table are listed in order of
rank, from highest to lowest priority. If two or more enabled
and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
from the interrupt service routine, the next highest-level
pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are en-
abled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in
the vector table. This is an unusual occurrence, and may be
the result of an error. It can legitimately result from a change
in the enable bits or pending flags prior to the execution of
the VIS instruction, such as executing a single cycle instruc-
tion which clears an enable flag at the same time that the
pending flag is set. It can also result, however, from inad-
vertent execution of the VIS command outside of the context
of an interrupt.
The default VIS interrupt vector can be useful for applica-
tions in which time critical interrupts can occur during the
servicing of another interrupt. Rather than restoring the pro-
gram context (A, B, X, etc.) and executing the RETI instruc-
tion, an interrupt service routine can be terminated by return-
ing to the VIS instruction. In this case, interrupts will be
serviced in turn until no further interrupts are pending and
the default VIS routine is started. After testing the GIE bit to
ensure that execution is not erroneous, the routine should
restore the program context and execute the RETI to return
to the interrupted program.
This technique can save up to fifty instruction cycles (t
c), or
more, (50 s at 10 MHz oscillator) of latency for pending
interrupts with a penalty of fewer than ten instruction cycles
if no further interrupts are pending.
To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Al-
though it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The
use of polling allows the standard arbitration ranking to be
altered, but the reliability of the interrupt system is compro-
mised. The polling routine must individually test the enable
and pending bits of each maskable interrupt. If a Software
Trap interrupt should occur, it will be serviced last, even
though it should have the highest priority. Under certain
conditions, a Software Trap could be triggered but not ser-
viced, resulting in an inadvertent 鈥渓(f膩)ocking out鈥� of all
maskable interrupts by the Software Trap pending flag.
Problems such as this can be avoided by using VIS
instruction.
TABLE 5. Interrupt Vector Table
Arbitration
Vector (Note 20)
Ranking
Source
Description
Address
(Hi-Low Byte)
(1) Highest
Software
INTR Instruction
0yFE鈥�0yFF
(2)
Reserved
Future
0yFC鈥�0yFD
(3)
External
G0
0yFA鈥�0yFB
(4)
Timer T0
Underflow
0yF8鈥�0yF9
(5)
Timer T1
T1A/Underflow
0yF6鈥�0yF7
(6)
Timer T1
T1B
0yF4鈥�0yF5
(7)
MICROWIRE/PLUS
BUSY Low
0yF2鈥�0yF3
(8)
Reserved
Future
0yF0鈥�0yF1
(9)
Reserved
Future
0yEE鈥�0yEF
(10)
Reserved
Future
0yEC鈥�0yED
(11)
Reserved
Future
0yEA鈥�0yEB
(12)
Reserved
Future
0yE8鈥�0yE9
(13)
Reserved
Future
0yE6鈥�0yE7
(14)
Reserved
Future
0yE4鈥�0yE5
(15)
Port L/Wakeup
Port L Edge
0yE2鈥�0yE3
(16) Lowest
Default
VIS Instruction
0yE0鈥�0yE1
Execution without any interrupts
Note 20: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last
address of a block. In this case, the table must be in the next block.
COP8SA
Family
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鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-B4Y-IX-F4 | CONVERTER MOD DC/DC 3.3V 49.5W |
| VE-B63-IY-F2 | CONVERTER MOD DC/DC 24V 50W |
| VE-B63-IY-F1 | CONVERTER MOD DC/DC 24V 50W |
| VE-B63-CU-B1 | CONVERTER MOD DC/DC 24V 200W |
| VE-B62-IY-F4 | CONVERTER MOD DC/DC 15V 50W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| COP8SAC5 | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| COP8SAC7 | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| COP8SAC720 | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| COP8SAC720M7 | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:8-Bit CMOS ROM Based and One-Time Programmable (OTP) Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| COP8SAC720M8 | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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