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| 型號(hào)： | COP8CSDR9KMT7 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁(yè)數(shù)： | 60/80頁(yè) |
| 文件大小： | 972K |
| 代理商： | COP8CSDR9KMT7 |
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17.0 MICROWIRE/PLUS
(Continued)
17.1.2.1 Alternate SK Phase Operation and SK Idle
Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Refer to
Table 25
for
the appropriate setting of the SKSEL bit. The SKSEL is
mapped into the G6 configuration bit. The SKSEL flag will
power up in the reset condition, selecting the normal SK
signal provided the SK Idle Polarity remains LOW.
TABLE 25. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
Port G
SO Clocked Out On:
SI Sampled On:
SK Idle
Phase
SK Phase
G6 (SKSEL)
Config. Bit
0
1
0
1
G5 Data
Bit
0
0
1
1
Normal
Alternate
Alternate
Normal
SK Falling Edge
SK Rising Edge
SK Rising Edge
SK Falling Edge
SK Rising Edge
SK Falling Edge
SK Falling Edge
SK Rising Edge
Low
Low
High
High
10138935
FIGURE 29. MICROWIRE/PLUS Application
10138936
FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
C
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