參數(shù)資料
型號(hào)： COP8CSDR9KMT7
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
中文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO56
封裝： TSSOP-56
文件頁數(shù)： 4/80頁
文件大?。?/td> 972K
代理商： COP8CSDR9KMT7
Table of Contents
(Continued)
12.1.1 ITMR Register .................................................................................................................................. 34
12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 35
12.2.1 Timer Operating Speeds .................................................................................................................. 35
12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 35
12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 36
12.2.4 Mode 3. Input Capture Mode .......................................................................................................... 36
12.3 TIMER CONTROL FLAGS .................................................................................................................... 36
13.0 Power Saving Features ............................................................................................................................ 37
13.1 POWER SAVE MODE CONTROL REGISTER .................................................................................... 38
13.2 OSCILLATOR STABILIZATION ............................................................................................................. 39
13.3 HIGH SPEED MODE OPERATION ...................................................................................................... 39
13.3.1 High Speed Halt Mode .................................................................................................................... 39
13.3.1.1 Entering The High Speed Halt Mode ......................................................................................... 39
13.3.1.2 Exiting The High Speed Halt Mode ........................................................................................... 39
13.3.1.3 HALT Exit Using Reset .............................................................................................................. 39
13.3.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 39
13.3.1.5 Options ....................................................................................................................................... 39
13.3.2 High Speed Idle Mode ..................................................................................................................... 40
13.4 DUAL CLOCK MODE OPERATION ...................................................................................................... 40
13.4.1 Dual Clock HALT Mode ................................................................................................................... 41
13.4.1.1 Entering The Dual Clock Halt Mode .......................................................................................... 41
13.4.1.2 Exiting The Dual Clock Halt Mode ............................................................................................. 41
13.4.1.3 HALT Exit Using Reset .............................................................................................................. 41
13.4.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 41
13.4.1.5 Options ....................................................................................................................................... 41
13.4.2 Dual Clock Idle Mode ...................................................................................................................... 41
13.5 LOW SPEED MODE OPERATION ....................................................................................................... 42
13.5.1 Low Speed HALT Mode ................................................................................................................... 42
13.5.1.1 Entering The Low Speed Halt Mode ......................................................................................... 42
13.5.1.2 Exiting The Low Speed Halt Mode ............................................................................................ 42
13.5.1.3 HALT Exit Using Reset .............................................................................................................. 42
13.5.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 42
13.5.1.5 Options ....................................................................................................................................... 42
13.5.2 Low Speed Idle Mode ...................................................................................................................... 42
13.6 MULTI-INPUT WAKE-UP ...................................................................................................................... 43
14.0 USART ..................................................................................................................................................... 44
14.1 USART CONTROL AND STATUS REGISTERS ................................................................................... 45
14.2 DESCRIPTION OF USART REGISTER BITS ...................................................................................... 45
14.3 ASSOCIATED I/O PINS ........................................................................................................................ 46
14.4 USART OPERATION ............................................................................................................................ 46
14.4.1 Asynchronous Mode ........................................................................................................................ 47
14.4.2 Synchronous Mode .......................................................................................................................... 47
14.5 FRAMING FORMATS ............................................................................................................................ 47
14.6 USART INTERRUPTS .......................................................................................................................... 48
14.7 BAUD CLOCK GENERATION .............................................................................................................. 48
14.8 EFFECT OF HALT/IDLE ....................................................................................................................... 50
14.9 DIAGNOSTIC ........................................................................................................................................ 50
14.10 ATTENTION MODE ............................................................................................................................. 50
14.11 BREAK GENERATION ........................................................................................................................ 50
15.0 Interrupts .................................................................................................................................................. 51
15.1 INTRODUCTION ................................................................................................................................... 51
15.2 MASKABLE INTERRUPTS ................................................................................................................... 51
15.3 VIS INSTRUCTION ............................................................................................................................... 52
15.3.1 VIS Execution .................................................................................................................................. 53
15.4 NON-MASKABLE INTERRUPT ............................................................................................................ 54
15.4.1 Pending Flag .................................................................................................................................... 54
15.4.2 Software Trap .................................................................................................................................. 54
15.4.2.1 Programming Example: External Interrupt ................................................................................. 56
15.5 PORT L INTERRUPTS .......................................................................................................................... 56
15.6 INTERRUPT SUMMARY ....................................................................................................................... 56
16.0 WATCHDOG/Clock Monitor ..................................................................................................................... 57
C
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