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參數(shù)資料
| 型號： | CLC5903SM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | Dual Digital Tuner / AGC |
| 中文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | BGA-128 |
| 文件頁數(shù)： | 7/29頁 |
| 文件大?。?/td> | 698K |
| 代理商： | CLC5903SM |
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C
AOUT
BOUT
82
78
G12
G10
SERIAL OUTPUT DATA,
Active high
The 2’s complement serial output data is transmitted on these pins, MSB first. The
output bits change on the rising edge of
SCK
(falling edge if SCK_POL=1) and should
be captured on the falling edge of
SCK
(rising if SCK_POL=1). These pins are
tri-stated at power up and are enabled by the SOUT_EN control register bit. See Fig-
ure 10 and Figure 30 timing diagrams. In Debug Mode
AOUT
=
DEBUG[1]
,
BOUT
=
DEBUG[0]
.
AGAIN[2:0],
BGAIN[2:0]
125:127
40:42
D4,A3,D5
J5,L4,M3
OUTPUT DATA TO DVGA,
Active high
3 bit bus that sets the gain of the DVGA determined by the AGC circuit.
ASTROBE,
BSTROBE
124
43
C4
K5
DVGA STROBE, Active low
Strobes the data into the DVGA. See Figure 9 and Figure 35 timing diagrams.
SCK
80
H11
SERIAL DATA CLOCK
, Active high or low
The serial data is clocked out of the chip by this clock. The active edge of the clock is
user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN
control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode out-
puts an appropriate clock for the debug data. If RATE=0 the input
CK
duty cycle will
be reflected to
SCK
.
SCK_IN
99
B11
SERIAL DATA CLOCK INPUT,
Active high or low
Data bits from a serial daisy-chain slave are clocked into a serial daisy-chain master
on the falling edge of
SCK_IN
(rising if SCK_POL=1 on the slave). Tie low if not used.
SFS
81
F9
SERIAL FRAME STROBE
, Active high or low
The serial word strobe. This strobe delineates the words within the serial output
streams. This strobe is a pulse at the beginning of each serial word (PACKED=0) or
each serial word I/Q pair (PACKED=1). The polarity of this signal is user programma-
ble. This pin is tri-stated at power up and is enabled by the SOUT_EN control register
bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode
SFS
=
DEBUG[2]
.
POUT[15:0]
84,86:88,
90,91,
93:97,104:
106,
108,109
F12,F10,
E11,E12,
D11,D12,
E9,C12,D9,
C11,B12,
B9,A10,C8,
D7,C7
PARALLEL OUTPUT DATA,
Active high
The output data is transmitted on these pins in parallel format. The
POUT_SEL[2..0]
pins select one of eight 16-bit output words. The
POUT_EN
pin enables these out-
puts.
POUT[15]
is the MSB. In Debug Mode
POUT[15..0]
=
DEBUG[19..4]
.
POUT_SEL[2:0]
112:114
D6,A7,B7
PARALLEL OUTPUT DATA SELECT,
Active high
The 16-bit output word is selected with these 3 pins according to Table 2. Not used in
Debug Mode. For a serial daisy-chain master,
POUT_SEL[2:0]
become inputs from
the slave:
POUT_SEL[2]
=
SFS
SLAVE
,
POUT_SEL[1]
=
BOUT
SLAVE
, and
POUT_SEL[0]
=
AOUT
SLAVE
. Tie low if not used.
POUT_EN
111
B8
PARALLEL OUTPUT ENABLE.
Active low
This pin enables the chip to output the selected output word on the
POUT[15:0]
pins.
Not used in Debug Mode. Tie high if not used.
RDY
77
G9
READY FLAG
, Active high or low
The chip asserts this signal to identify the beginning of an output sample period
(OSP). The polarity of this signal is user programmable. This signal is typically used
as an interrupt to a DSP chip, but can also be used as a start pulse to dedicated cir-
cuitry. This pin is active regardless of the state of SOUT_EN. In Debug Mode
RDY
=
DEBUG[3]
.
CKA,
CKB
20,
38
F2
K4
INPUT CLOCK.
Active high
The clock inputs to the chip. The corresponding
AIN
and
BIN
signals are clocked into
the chip on the rising edge of this signal.
CKA
and
CKB
are OR’d together on chip to
create the
CK
signal.
SI
is clocked into the chip on the rising edge of
CK
. Tie low if not
used.
SI
46
J6
SYNC IN.
Active low
The sync input to the chip. The decimation counters, dither, and NCO phase can be
synchronized by
SI
. This sync is clocked into the chip on the rising edge of
CK
(
CK
=
CKA
+
CKB
). Tie this pin high if external sync is not required. All sample data is
flushed by
SI
. To properly initialize the DVGA
ASTROBE
and
BSTROBE
are asserted
during
SI
.
Pin Descriptions
(Continued)
Signal
PQFP Pin
FBGA Pin
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CLC5903SM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5955 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
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